High-Performance DSPs -> New Needs and Applications Drive DSPs

New Needs and Applications Drive DSPs
By John Setel O'Donnell, Co-Founder and, Chief Technology Officer, Equator Technologies Inc., Campbell, Calif., EE Times
November 15, 2001 (3:41 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011115S0057

Just over a decade ago, POTS line modems delivered 9,600 baud, at most, in the dial-up voice channel. Their modulation and compression functions were implemented by ASICs. Three years later, DSP-based modems were delivering more than three times the data rate in the same voice channel; shortly thereafter, another doubling of the data rate was delivered using the same DSP hardware.

When modem developers moved their core algorithms from hardware to DSP software implementations, they were able to conceive and deliver more complex algorithms that extracted more from the channel, and their new algorithms were brought to market faster. As a result, DSP-based modems captured essentially 100 percent of the world market within four years of their market entry. Today, multiple products, ranging from the cellular phone to the MP3 player, have been made possible by similar "simple DSP" technology.

Today's DSP landscape sees straightforward extensions of t he voice and data communications applications of a decade ago. Devices run at higher density, lower cost and lower power per channel. Cellular basestations, modem concentrators, audio and similar applications have been addressed by this evolutionary improvement.

New applications have become practical as DSP performance has increased. Examples include image processing in office equipment (copiers and printers), video security, network multimedia, videoconferencing, streaming video, HDTV and digital video recorders, and physical-layer signal processing in high-speed and wireless communications. Rising processor power has opened these problem areas to software-based solutions, allowing ASIC development cycles to be skipped and allowing more complex, variable, adaptive processing techniques to be incorporated in these devices.

Such applications are driving a need for much more powerful DSP platforms. Standard-definition digital video compression, for example, requires more than 100 times the DSP proces sing power needed for cell phone voice compression or POTS data modem functions.

Along with the need for more processing power, significant improvements in software development methodologies are urgently needed to support the new applications. The DSP approach of a decade ago, where assembly-language core algorithm development was augmented with some high-level language control software (which ran at low efficiency), is a poor match for today's shorter product development cycles, expectations of richer product functionality and more complex fundamental algorithms.

As we move beyond the classic approach to DSP to higher-performance designs, there is a wide spectrum of alternatives to consider. The first dimension is single-processor vs. multiprocessor. Several vendors offer multiple-processor approaches to high-performance DSP. Instead of building a single high-performance processor, an array of medium-performance processors is provided as a single-chip solution. The approach greatly simplifies the DSP chip developer's task, reducing it to a medium-performance design with a "step-and-repeat" layout. At the same time, however, it greatly complicates the application software developer's task.

To extract performance from an array of processors, numerous problems in task distribution, communications overhead vs. computation, and load balancing must be solved. Programming of the core loops becomes only a small portion of the overall development. As algorithms become more sophisticated and adaptive, the problem becomes even more severe.

For problems with substantial data independence or with the ability to carry out computations on multiple data elements with minimal dependencies or communication among elements, array-style DSPs may be worth considering. For other problems, the engineer should first seek a fast single processor to meet the need.

Over time, improvements in semiconductor fabrication have improved the available clock rate for existing architectures. Frequency scaling is limited by fixed relationships between memory and logic speeds, and unbalanced improvements limit overall improvement. As a result, new architectures have been developed to go beyond the classic one-MAC DSP. They include simple extensions of the "classic DSP," architectures that incorporate new features designed to speed a class of problems, and even architectures designed primarily for a particular task.

Fundamental tools available to the DSP architect include:

• Multiple instruction issue. Instead of issuing and executing one instruction per clock, the DSP can issue and execute multiple instructions. Many desktop processors today use "superscalar" architecture to implement multiple instruction issue; however, in many cases, more than 70 percent of the on-chip logic transistors are consumed with superscalar instruction parsing and operation scheduling, making the superscalar approach far too expensive for DSP-type applications.

  Very long instruction word (VLIW) architecture provides a framework fo r issuing and executing multiple arbitrary instructions per clock cycle at the lowest possible hardware cost. In a "pure" VLIW, all machine management is handled by the compiler or the assembly language developer. VLIW architectures can directly deliver two- to eightfold performance improvements over single-issue DSPs, on a wide range of algorithms — at the cost of greatly increased demands on the compiler or significantly increased assembly language development complexity.

• SIMD architecture. Single-instruction multiple-data (SIMD) ideas have shown up in many modern architectures. Here, the same instruction operates on multiple data elements. In some cases they are full-word data types; in other cases they are shorter data elements packed into a longer word size. SIMD techniques reduce instruction code size and simplify execution unit design for regular algorithms, in which many operations are applied in a pattern that can be organized into one machine instruction.

• Deep pipelines. Old er DSPs carry out a register or memory read, arithmetic operation chain and register write in a single clock period, enabling "single-cycle loops" and simplifying assembly language programming. The trade-off is relatively low clock frequency. With modest area changes, a machine can be re-pipelined to separate the register read, arithmetic operations and register write into separate clock periods, thereby enabling a significantly faster clock and higher cost-effectiveness.

  The cost of deep pipelines shows up in complex pipeline latency management at the assembly-code level, thus increasing the demand for a highly effective compiler.

• Application-optimized resources. In a "pure" DSP or RISC processor, each operation fetches values from general registers, carries out a single operation and stores the result back to registers. In many cases, the register file consumes more power and chip area than the attached computation unit.