FPGA-based rapid prototyping of ASIC, ASSP, and SoC designs
By Juergen Jaeger, Synopsys Inc.
pldesignline.com (October 21, 2009)
ASIC designs continue to increase in size, complexity, and cost (for the purpose of these discussions, the term ASIC is assumed to encompass ASSP and SoC devices). At the same time, aggressive competition makes today's electronics markets extremely sensitive to time-to-market pressures. Furthermore, market windows are continually narrowing; in the case of consumer markets, for example, a "typical" ASIC design cycle is in the order of 9 to 18 months, while the window of opportunity for the introduction of a product using this device can be as little as 2 to 4 months.
Failing to have a product available at the beginning of the intended market window may result in significantly reduced revenue (or a complete loss of revenue and investment if the window is missed in its entirety). These factors have dramatically increased the pressure for ASIC designs to be "right-first-time" with no re-spins. In turn, this has driven the demand for fast, efficient, and cost-effective verification at both the chip and system levels.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related White Papers
- How to improve FPGA-based ASIC prototyping with SystemVerilog
- ASIC vendors heed call for virtual prototyping tools
- How to use on-target rapid prototyping
- A Novel Modeling and Verification Environment for Rapid IP Prototyping
Latest White Papers
- New Realities Demand a New Approach to System Verification and Validation
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- Sustainable Hardware Specialization
- PCIe IP With Enhanced Security For The Automotive Market
- Top 5 Reasons why CPU is the Best Processor for AI Inference