Choosing an effective embedded SoC ASIC design strategy
Sunit Bansal, Freescale Semiconductor Inc.
EETimes (12/13/2010 8:18 PM EST)
In large and complex system-0n-chip ASIC design, two of the most challenging tasks are those involving design closure, timing routing and power.
It is a tedious task to converge on timing and routing, owing to the limitations of design size and the memory-intensive calculations. Essentially, it is dependent on the design size that an EDA tool can handle.
In such cases, it is advisable to go for a hierarchical approach instead of a flat top. Generally, the blocks are demarcated on the basis of functionality, backward compatibility, third party IP etc.
This article details the difference in terms of runtimes, routing congestion, timing summary and utilization for a design that is done as hierarchical vs. the same design using the flat approach.
To read the full article, click here
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related White Papers
- Optimize SoC Design with a Network-on-Chip Strategy
- FPGA to ASIC Strategy for Communication SoC Designs
- Picking the right built-in self-test strategy for your embedded ASIC
- An Efficient Device for Forward Collision Warning Using Low Cost Stereo Camera & Embedded SoC