Embedded EE Array Grows a BISTy Core

Embedded EE Array Grows a BISTy Core
By Clifford R. Warren, Integrated System Design
March 1, 2002 (12:29 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020227S0053

MI Semiconductor has developed for its smaller-geometry processes several types of nonvolatile memory macrocells, including a nonvolatile latch for situations that require a very small amount of nonvolatile memory; a serial array; and a full EE array with cells organized in rows and columns, much like a typical SRAM. A special "no-added-fab-steps" technique allows this to be done in a low-cost manner. Electrically erasable memory technology holds several advantages over flash memory when embedded in an ASIC. While flash memory has a higher density, the added processing step and lowered reliability limit its use in ASIC designs. Typical SRAM and DRAM designs can have millions of bits, and the algorithms used to test them are commonly called "March tests." However, the long programming times of an EE array severely limit the use of these tests. These nonvolatile memory devices require high voltages (around 20 V) and long programming times to write data t o the core. This can be on the order of 10 milliseconds. If we assume that the typical write time to an SRAM is on the order of 10 nanoseconds, then the program times for the array are 1 million times longer. The length of this programming time requires a new approach to test.

As the EE array is embedded into a highly customized chip, test becomes an issue that must be dealt with. When an embedded macrocell is used, the inputs and outputs of the cell are likely to be buried deeply within the chip. In cases like these, built-in self-test is used to test these structures, much as BIST is the technology of choice to test embedded SRAM and DRAM.

This article presents a "distributed-test" approach that tests several portions of the array separately. For example, we will test the row address decoders, column address decoders and control circuitry without using programming steps. When writing to the core, we will make use of several programming modes that allow us to program large portions of the array in ju st one programming step. As in most good approaches to test, the capability to test begins with the design of the device to be tested.

Design built in
The EE array has a 4-bit mode selector. These modes are summarized in Table 1. Several of the modes have been created specifically to aid in the testing of the array. For example, modes 6 and 7, "Read Test ROM Rows" and "Read Test ROM Columns," are provided to enable quick testing of the address circuitry, large portions of the control circuitry and of the sense amps. The "even/odd page write and erase" and "block write and erase" functions will also be used to aid testing. These special functions are critical to achieving an efficient test.

The array allows for independent testing of the data latches (scratchpad RAM) separately from the core. In the BIST, the data latches are completely verified before processing to the more lengthy tests of the core.

One page at a time
The AMIS 8Kx8 EE array is arranged into 256 rows and 256 columns. Each row is referred to as a "page," and in normal use the array is written to one page at a time. The array macro includes a 32 x 8 scratch RAM (256 bits) that can be written to like a typical SRAM, and this data can then be programmed into one page of the array.

But in addition to the 256 rows and 256 columns, this design includes an extra four rows (two on the top, two on the bottom) and four columns (two on each side) of ROM (see Fig. 1). This ROM is used to test the row and column addressing. By carefully selecting the data that is stored in these ROMs, and using the existing row and column address decoding to select this data, we can determine the correctness of the row and column circuitry. Of course, since this is a ROM, this test is now performed without the need for lengthy program cycles. The ROM can be tested with the BIST method, by using typical ROM BIST techniques.

The 8Kx8 array makes use of a 32 x 8 s cratchpad RAM. This 256-bit RAM can be written to at high speed, like a normal SRAM. In normal operation, the user would write data to this RAM, then use a lengthy programming step to write a page (a 256-bit row) to the array. The next step in our strategy is to verify this small RAM.

We accomplish this with our BIST approach by writing a pattern and reading it by using normal RAM BIST techniques. Note that the mode selection of the array macro allows this-that is, it allows one to read from the latch-based RAM directly. Thus, we write and read checkerboard and inverse-checkerboard patterns from the RAM.

Now, with addressing tests complete and the latch-based RAM tests complete, we turn our attention to the array core. Again, the following special modes to aid in testing are built into the EE array: