Dual core architectures in automotive SoCs
Amit Goel & Ankur Sharma, Freescale Semiconductor
EETimes, 8/23/2010 2:17 PM EDT
Automotive SoCs have traditionally been single core, since not much computational work or high end applications were targeted on them. Automotives were simpler, so were the applications and so were the SoCs. As more and more electronics made room in the automotives, the complexity of the SoCs kept on increasing. Now the focus is to have most of the automotive under electronic control.
High end automotives produced these days provide features like electronic stability control (ESC), traction control system (TCS), advanced driver assistance systems (ADAS) etc. These features require complex SoCs at heart which can collect, process and transfer data at a fast rate from multiple peripherals.
No matter at how much high frequency the single core is operating on, it will always have performance bottlenecks & challenges while performing multiple tasks. Single core running on higher frequency consumes more power. This makes the single core architecture unfit for ultra low power applications. Dual core based SOC architecture provide better tradeoff in performance and power consumption than single core based architectures.
To read the full article, click here
Related Semiconductor IP
- NPU IP Core for Mobile
- V-by-One® HS plus Tx/Rx IP
- MSP7-32 MACsec IP core for FPGA or ASIC
- 100G / 200G / 400G / 800G / 1.6T MACsec
- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
Related White Papers
- An IP core based approach to the on-chip management of heterogeneous SoCs
- Choosing between dual and single core media processor configurations in embedded multimedia designs
- Verification of IP Core Based SoC's
- Leverage UML and SysML in designing automotive software application architectures
Latest White Papers
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design
- CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
- Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions