Control an FPGA bus without using the processor

Noe Quintero, Linear Technology
EDN (April 27, 2016)

Many FPGA designs use an embedded processor for control. A typical solution involves the use of a soft processor such as a Nios, though FPGA SoCs with a built-in hard processor have become popular too. Figure 1 shows a typical Altera FPGA system that contains the processor and a mix of peripherals that are connected via Altera’s Avalon Memory Mapped (MM) bus. These processors greatly simplify the end application, but require a strong programing background and knowledge of complicated toolchains. This can hinder debug, especially if a hardware engineer needs a simple way to read and write to the peripherals without pestering the software engineer.

This Design Idea uses Altera's SPI Slave to Avalon MM Bridge to provide a simple way to hop onto the Avalon bus. There are two advantages to this technique: It does not compromise the original system design, and the bridge can co-exist with the embedded processor. For the system shown in Figure 1, the SPI bridge allows the engineer to directly control the frequency of the LTC6948 fractional-N PLL, set the LTC1668 DAC voltage, read a voltage from the LTC2498 ADC, or read temperatures from the LTC2983, just like the processor can.

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