How to accelerate genomic sequence alignment 4X using half an FPGA
Alexandre Cornu, Steven Derrien, and Dominique Lavenier, INRIA / IRISA, Rennes, France
7/5/2011 3:00 PM EDT
Designing FPGA-based accelerators is a difficult and time-consuming task that can be eased by High Level Synthesis Tools. To illustrate, we describe how a C-to-hardware methodology has been used to develop an efficient systolic array for the genomic sequence alignment problem. We also compare design performance with traditional HDL implementations.
FPGA gate density is doubling approximately every two years. Consequently, increasingly complex designs can be integrated into a single FPGA, which can now be considered as a high-power computing accelerator. However, pushing processing into such devices can lead to development time and design reliability issues. Recent efforts have helped FPGA-targeted application designers deal with large amounts of resources. In particular, Electronic System Level tools provide a higher level of abstraction than traditional HDL design flows. Several High Level Languages (HLL) for modeling complex systems, and corresponding High Level Synthesis (HLS) Tools to translate HLL-based designs into HDL synthesizable projects are available. Most of them are based on a subset of C/C++ [1] generally extended with specific types or I/O capabilities. Here we focus on the C to FPGA tool set [3] and its associated flow.
To read the full article, click here
Related Semiconductor IP
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- Neuromorphic Processor IP
Related White Papers
- Using Multi-Gigabit Transceivers to Test and Debug FPGA
- Using parallel FFT for multi-gigahertz FPGA signal processing
- Control an FPGA bus without using the processor
- How to tackle serial backplane challenges with high-performance FPGA designs
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS