The Tradeoffs of Low Dropout (LDO) Voltage Regulator Architectures and the Advantages of "Capless" LDOs

Originally written by: Edgar Sanchez-Sinencio, Ph.D. and Jerry Rudiak (Vidatronic, Inc.)
Revised: January 2019 by Stephen M. Nolan (Vidatronic, Inc.)

ABSTRACT

Power management of battery-powered electronic devices is becoming increasingly more important for the microelectronics industry. This white paper details the difference between low dropout (LDO) voltage regulators that use external output capacitors and those that do not, and how your system designs can benefit from not using an output capacitor. Well-designed capless LDO voltage regulators can have multiple benefits, and they are presented here.

INTRODUCTION

The demand for battery-powered electronic devices with better performance and higher efficiency continues to increase, driving engineers to design systems that provide best-in-class performance, while consuming minimal power. Subsequently, the power management of such devices is increasingly more important for the microelectronics industry. For systems to be successful in the market, it is vital to increase the operating time of the device and the battery while reducing the total system cost.

The power supplies in complex systems are divided into multiple power domains to provide noise isolation as well as to improve power efficiency with options to turn on/off different power islands. Therefore, an increasing number of voltage regulators are required. The low drop-out (LDO) voltage regulator is often used to provide a stable and highly-accurate low-noise output voltage. The LDO voltage regulator can be in a standalone Power-Management Integrated Circuit (PMIC), or an embedded circuit within a System on a Chip (SoC).

A typical LDO voltage regulator normally requires an external capacitor. This external capacitor is usually necessary to have acceptable transient response, power supply noise rejection (PSR), and stability of the LDO. The external capacitor, however, is usually bulky, occupies valuable board space, decreases long-term reliability, and consumes valuable pins in SoC devices. Additionally, the practical selection of a real capacitor that meets all the requirements of the LDO over a broad range of operating conditions can be very difficult. An ideal solution would not require an external capacitor.

Some LDO voltage regulators use architectures that do not require the external load capacitance. These are referred to as “capacitor less”, “capless”, and “capacitorfree”. The absence of the external capacitor brings many economic advantages; however, significant degradation can often be seen in areas of transient performance and power supply noise rejection. As a result, significant design challenges accompany the capacitor-free LDO voltage regulator that must be economically and efficiently overcome. The tradeoffs of LDO voltage regulator architectures and the advantages of “capless” LDOs are presented below.

LDO VOLTAGE REGULATOR ARCHITECTURES

A typical LDO voltage regulator consists of a voltage reference, an error amplifier, a pass transistor, and a resistor feedback. The output voltage of the regulator is fed back as one of the inputs to the error amplifier. Therefore, LDO voltage regulators are a closed-loop architecture circuit.

Because feedback exists, a poorly designed voltage regulator can become unstable in response to a transient condition at the input or output and can produce ringing or, worst-case, continuous oscillations at the output.

When designing a voltage regulator, loop-response analyses must be done to ensure stable operation. Gain and phase margin are two important loop stability analyses that are considered in any good regulator design.

LDO VOLTAGE REGULATORS WITH EXTERNAL LOAD CAPACITORS

Traditional LDO voltage regulators use off-chip output capacitors in the range of a few microfarads. This topology has one dominant pole at the output, which yields good stability in the loop-response analyses. Offchip capacitors also contribute to good power-supply noise rejection, line regulation and load regulation.

There are, however, several practical concerns that must be considered when selecting external output capacitors in those applications where they are required.

External, discrete capacitors have non-idealities that can be critical. There is a parasitic Effective Series Inductance (ESL), and a parasitic Effective Series Resistance (ESR). Both ESL and ESR decrease the capacitor’s performance at high frequency.

Figure 1. External Capacitor Model

There exist several elaborate models of a real capacitor. In Figure 1, above, we include a relatively simple model of a real capacitor to illustrate its nature. It consists of four impedances, connected as shown. The impedance on the left is the ESR, the middle is the ideal capacitor connected in parallel with a large leakage resistor, and on the right is the ESL. The behavior of this model for low and high frequencies relative to the resonance frequency, ωo, is also illustrated.

The reactance of an ideal capacitor is 1⁄2????????????, which decreases as frequency increases. At very high frequencies, the reactance of the capacitor can become very small. When doing a loop stability analysis of a traditional regulator, it can be found that if the impedance is too small, the dynamic response can be degraded, as this becomes a dominant pole that can dramatically reduce phase margin. However, as shown in the model above, the total impedance includes both the reactance of the capacitance and the ESR. Therefore, a minimum ESR is usually needed so that the total impedance doesn’t go to zero at high frequencies.

Unfortunately, a large ESR can create a zero that extends the unity gain frequency in the closed loop, yielding a larger unity gain frequency but severely deteriorating the phase margin, making the system unstable. While the minimum ESR is a concern, the maximum ESR is the more critical value to ensure stable operation.

To satisfy stability, LDO voltage regulator manufacturers impose restrictions on the ESR of the output capacitance, requiring it to be bounded within a specific range of minimum and maximum values.

Furthermore, these stability analyses should consider that the capacitor non-idealities are sensitive to mechanical effects, and vary with bias and temperature. Capacitance variation over temperature can be ±20% or more. ESL and ESR are usually not specified versus temperature or given a target tolerance; however, they can vary widely, causing their impact over temperature on loop dynamics to be extreme. The lack of specification adds risks to the LDO voltage regulator system operation because it becomes difficult for the user to guarantee that the LDO voltage regulator will work over all operating conditions.

You can see that the capacitor non-idealities must be carefully considered in conventional LDO voltage regulator designs. This makes selection of a real capacitor for use in the application a difficult challenge. It should be noted that an incorrect selection of the external load capacitor might lead to stability problems, excessive power dissipation, and noise, which will all reduce the battery and product life.

LDO voltage regulator applications use three main types of capacitors: ceramic, tantalum, and in some larger power applications, aluminum electrolytic. Different capacitor technologies have different performance capabilities and costs. Ceramic capacitors are the most common capacitors used in LDO voltage regulator applications for their low cost and reduced footprint size.

Ceramic capacitors typically have much lower ESL and ESR (in the range of several 10s of milliohms, compared to tantalum capacitors which typically have an ESR in the range of 100s of milliohms) and therefore work better at high frequencies, but they are also usually available only in smaller capacitance values. For this reason, it is common, to use a large-value electrolytic or tantalum capacitor for bulk capacitance, and to add a small ceramic capacitor in parallel to allow highfrequency bypassing of the bulk capacitor, thus extending the useful frequency range of the external capacitance. Where a tantalum capacitor is used, its ESR is more sensitive to temperature variations, forcing designers to anticipate how to compensate for this perturbation.

There are other factors that should be considered when selecting the output capacitor besides the ESR. For example, failure modes. Ceramic capacitors typically behave as an open circuit when they fail, while tantalum capacitors typically fail shorted. These considerations contribute to the complexity of designing reliable circuits when discrete external capacitors are required.

In practice most LDO voltage regulators can only guarantee stability for a specific output capacitance range. However, there are often real, practical situations where the load capacitance of the device to be powered by the LDO voltage regulator is not known in advance. In such cases, LDO voltage regulators are required to properly operate with a wide range of capacitance loads, from near-zero to several microfarads.

Capacitors have board real estate and economic cost implications. Furthermore, for multiple reasons explained above, selecting output capacitors for reliable operation can be very difficult. Therefore, we should explore the use of capless LDO voltage regulators and their advantages and limitations.

CAPLESS LDO VOLTAGE REGULATORS

The capless LDO voltage regulator is appealing for both discrete and SoC integrated applications. The absence of the external load capacitance is extremely attractive since this can translate into a reduced printed circuit board (PCB) area and lower Bill-of-Materials (BOM) costs. Additionally, one less capacitor is one less device that can fail and does not need to be soldered.

In SoC applications where the LDO is integrated on-die, the savings and benefits are even greater due to the reduction of external pins as well as pad and package connections and their associated cost and electrical impedance considerations.

Figures 2 and 3 depict the differences between LDO voltage regulators with an off-chip capacitor and capless LDO voltage regulators.

Figure 2. LDO Voltage Regulator with Off-Chip Capacitor

Figure 3. Capless LDO Voltage Regulator

Eliminating the external capacitor also brings elimination of the metal paths, bond wires, and PCB traces. In addition, the concerns about the severe non-idealities of the discrete capacitors such as ESR and ESL are irrelevant.

Multiple LDO voltage regulators are usually used in complex systems; therefore, not needing to use external capacitors has a multiplier effect on these benefits.

The conventional off-chip capacitor LDO voltage regulator depends heavily on the external capacitor for its stability and performance. This voltage regulator has a dominant pole at the output node and can be designed to be stable for a specific load capacitance and bounded range of ESR and ESL. The capless LDO voltage regulator doesn’t have an output dominant pole but rather an internal dominant pole varying with the load current. Providing a stable LDO voltage regulator under any load current range and any load capacitor range (from no capacitor up to a few microfarads) is a challenging design problem.

Several solutions have been proposed for capless LDO voltage regulators, but they are functional under only a limited range of output current and/or load capacitance. Keep in mind that various applications can present a very wide range of load capacitance to the LDO voltage regulator, from extremely low to a large capacitance of the order of a few microfarads. A practical and robust capless LDO voltage regulator must be stable under all those extreme scenarios.

There have been attempts in the academic world and the industrial sector to provide a practical capless LDO voltage regulator, but many of the architectures have severe limitations, preventing their practical use. Several reported in literature obtain decent results, but only for a specific parameter such as load regulation, line regulation, or settling time. The large majority can only guarantee stability for a narrow range of load capacitance, between 0 pF to 100 pF, and a maximum load current of less than 100 mA. They also suffer significant losses in areas of dynamic performance and PSR effectiveness.

There is, however, one capless LDO voltage regulator architecture existing in the market today that provides true capless operation as well as low quiescent current, low dropout voltage, better than 1% output voltage accuracy, >40dB power supply noise rejection (PSR) at 10 MHz, and best-in-class dynamic load and line transient performance all while providing unconditional stability regardless of the capacitance of the load.

Vidatronic, Inc has developed an advanced-architecture capless LDO voltage regulator that is unconditionally stable, with or without output capacitance up to 4.7 μF. Using their patented Noise Quencher® technology, Vidatronic LDO voltage regulators are able to obtain best-in-industry transient performance and PSR, all without requiring output capacitance. These advantages make this family of LDO voltage regulators the optimum choice for SoC and system designers alike.

CONCLUSION

In this paper, we have presented the disadvantages of LDO voltage regulators that require the use of external output capacitors, and the advantages that capless LDO voltage regulator architectures provide SoC or system designers in terms of cost and board area savings.

For more information on Vidatronic’s advancedarchitecture LDO voltage regulators, power switches, and voltage references & regulators, go to: http://www.vidatronic.com/ip-solutions/.

FURTHER READING

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