Boundary scan and JTAG emulation combine for advanced structural test and diagnostics
By Heiko Ehrenberg & Thomas Wenzel (Goepel Electronics Ltd.)
EE Times Europe (11/10/09, 04:02:00 AM EST)
While continuously improving IC and SOC technologies, higher clock rates, and more powerful processors are music to the design engineers' ears, the headaches of test engineers are getting worse and worse.
The ever decreasing test access was the worrying factor in the past, but a new problem arose in recent years with the dramatically increasing speed of the signal transmission.
The resulting failure phenomena and test access limitations have an inevitable impact on the efficiency and practicality of test strategies.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related White Papers
- Signal Integrity --> LVDS extends utility of 1149.1 boundary scan test
- Processor Know Thyself: moving beyond on-chip JTAG emulation
- Boundary scan: Seven benefits
- ESC: Real-time analysis provides transport support for scan-based emulation
Latest White Papers
- New Realities Demand a New Approach to System Verification and Validation
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- Sustainable Hardware Specialization
- PCIe IP With Enhanced Security For The Automotive Market
- Top 5 Reasons why CPU is the Best Processor for AI Inference