API-based verification: Effective reuse of verification environment components
Bipin Patel & Manzil Shah (eInfochips)
EDN -February 22, 2017
Verification using various methodologies has become popular as it saves VE development time. Even more time can be saved if we think of possible reuse of various VE components when defining the VE architecture. The reuse of VE components at different levels is crucial to time-saving during design verification, with applications comprising block, cluster/subsystem, chip, or SoC levels, and can also result in huge time savings during post-silicon lab validation.
This paper talks about an API- (Application Program Interface) based verification approach that can be adopted for a whole segment of ASIC applications.
Let’s focus on design blocks B1, B2, and B3 of the example SoC in Figure 1. These blocks are interconnected using unique interfaces and each one of them is to be verified independently at the block level followed by cluster and chip levels.
To read the full article, click here
Related Semiconductor IP
- Audio Sample Rate Converter
- 1-56Gbps Serdes - 7nm (Multi-reference Clock)
- 1-56Gbps Serdes - 7nm (Ultra Low Latency)
- 1-56Gbps Serdes - 7nm (Area-optimized)
- 1-112Gbps Serdes - 7nm
Related White Papers
- Are we too Hard for Agile?
- Supporting hardware assisted verification with synthesizable assertions
- Digital Signal Processing (DSP) Verification
- Verification care abouts for SoC internal channel characterization using an ADC