API-based verification: Effective reuse of verification environment components
Bipin Patel & Manzil Shah (eInfochips)
EDN -February 22, 2017
Verification using various methodologies has become popular as it saves VE development time. Even more time can be saved if we think of possible reuse of various VE components when defining the VE architecture. The reuse of VE components at different levels is crucial to time-saving during design verification, with applications comprising block, cluster/subsystem, chip, or SoC levels, and can also result in huge time savings during post-silicon lab validation.
This paper talks about an API- (Application Program Interface) based verification approach that can be adopted for a whole segment of ASIC applications.
Let’s focus on design blocks B1, B2, and B3 of the example SoC in Figure 1. These blocks are interconnected using unique interfaces and each one of them is to be verified independently at the block level followed by cluster and chip levels.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- CXL 3.0 Controller
- ECC7 Elliptic Curve Processor for Prime NIST Curves
Related White Papers
- Digital Signal Processing (DSP) Verification
- Verification care abouts for SoC internal channel characterization using an ADC
- Verification challenges of ADC subsystem integration within an SoC
- Can Hardware-Assisted Verification Save SoC Realization Time?
Latest White Papers
- TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
- Enabling Chiplet Design Through Automation and Integration Solutions
- Shift-Left Verification: Why Early Reliability Checks Matter