Virage offers nonvolatile RAM to integrate on an SoC
Virage offers nonvolatile RAM to integrate on an SoC
By Jeanne Graham, EBN
February 22, 2002 (2:45 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020222S0048
Virage Logic Corp. today will unveil a product that allows system designers to reduce bills of materials by integrating small amounts of nonvolatile memory on an SoC using a standard logic process. Novea RAM, the first in Virage's new embedded-memory line, retains its contents at power-off while allowing data to be reprogrammed and erased. “This duplicates the circuit technology of flash [memory] on a standard logic process without extra mask layers,” said Vin Ratford, vice president of marketing and business development at the Fremont, Calif., IP vendor. Available on Taiwan Semiconductor Manufacturing Co. Ltd.'s 0.18-micron process, and 0.13-micron later this year, Novea RAM addresses applications such as set-top boxes, chip identification, and electrical metering equipment. Designers can choose the size and shape of the nonvolatile memory from a density of a few hundred bits up to 16Kbits, Ratford said. Given the product's low density , Virage expects the new memory will typically be used to replace EEPROM. About 1.5 billion EEPROM units were shipped last year, and about 85% of those units had densities of 16Kbits or less, Ratford said. Electrically, however, Novea RAM is more like flash memory, which means designers also have an alternative to low-density embedded flash, he said. “It's one of those innovative techniques that would allow you to easily integrate another little piece of the SoC picture,” said Jim Feldhan, an analyst at Semico Research Corp., Phoenix. “Why have another tiny package sitting off the chip, when now you can integrate it and there's no real penalty?” Novea RAM is currently designed for 1,000 write operations at speeds of 100ms, regardless of the memory size. An on-chip charge pump of 7 to 12V allows users to write to the memory in the field. License fees for Novea RAM range from $100,000 to $500,000 for pure-play foundries. An additional royalty is assessed per chip, Virage said.
Related Semiconductor IP
- ISO/IEC 7816 Verification IP
- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- Simulation VIP for AMBA CHI-C2C
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
Related News
- Virage Logic Embedded Multi-Time Programmable Non-Volatile Memory Gains Acceptance in Military Applications
- Virage Logic Unveils One Mega-Bit Embedded Reprogrammable Non-Volatile Memory (NVM) on Standard CMOS Process
- Virage Logic Acquires Impinj's Logic Non-Volatile Memory (NVM) IP Business
- Analog Devices Selects Virage Logic's AEON(R) Non-Volatile Memory Technology for High-Reliability Applications
Latest News
- Quintauris and Andes Technology Partner to Scale RISC-V Ecosystem
- Europe Achieves a Key Milestone with the Europe’s First Out-of-Order RISC-V Processor chip, with the eProcessor Project
- Intel Unveils Panther Lake Architecture: First AI PC Platform Built on 18A
- TSMC September 2025 Revenue Report
- Andes Technology Hosts First-Ever RISC-V CON in Munich, Powering Next-Gen AI and Automotive Solutions