Veriest collaborates with MINRES on RISC-V development
Joint work will enable early development of embedded software on RISC-V cores and safety-aware platforms
September 5, 2019 -- Veriest Solutions, a leading international Electronics Design Services house, and MINRES Technologies, a provider of next-generation Virtual Prototype solutions announced today a collaboration framework.
Under this collaboration, the companies will work to provide services and develop Virtual Prototyping solutions for RISC-V based systems, that allow to utilize state of the art software development paradigms (e.g. test driven design, continuous integration, agile development), resulting overall in increased productivity, reduced time-to-market, and most notably in the improvement of critical embedded system quality metrics, such as functional safety and security.
Furthermore, the companies will co-develop customized design environments that enable customers to create Safety-aware RISC-V platforms, under ISO26262 standard, leveraging Veriest expertise in the ASIC design and verification domains and MINRES expertise in Virtual Prototyping and Functional Safety.
Moshe Zalcberg, CEO of Veriest, said: “RISC-V is receiving increasing attention from our international clients. Through this collaboration with MINRES highly professional team, we will offer an extended RISC-V solution for our customers’ projects, leveraging on Veriest expertise in ASIC Design, Verification and Embedded Software”.
Eyck Jentzsch, General Manager of MINREs, added: “We are excited to collaborate with Veriest, a recognized leader in ASIC engineering services. This partnership will enable us to bring MINRES’ innovative solutions to a wider customer base”.
MINRES is a startup pioneering the development of next generation, cost-efficient Functional Safety compliant Virtual Prototyping and RISC-V IP solutions for the rapidly increasing number of safety critical embedded system applications. MINRES is a privately held company based in Munich, Germany.
MINRES will be presenting a session about “Embedded Software Development for RISC-V Based SoC” at the upcoming RISC-V Roadshow on September, 16, 2019, at Dan Tel Aviv Hotel, Israel.
For additional details, see: https://events.linuxfoundation.org/events/risc-vtelaviv2019/
Related Semiconductor IP
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
- All-In-One RISC-V NPU
Related News
- Socionext Announces Collaboration with Arm and TSMC on 2nm Multi-Core Leading CPU Chiplet Development
- NEDO Approves Rapidus' FY2024 Plan and Budget for "Research and Development of 2nm-generation semiconductor integration technology and short TAT manufacturing technology based on Japan-US collaboration"
- Openchip, NEC and Barcelona Supercomputing Center studying Collaboration to develop Next Generation Supercomputers based on RISC-V
- What RISC-V Means for the Future of Chip Development
Latest News
- Analog Bits Adds New Power and Energy Management IP Blocks Proven on TSMC N2P and N3P Processes at TSMC 2025 OIP Ecosystem Forum
- EnSilica and Codasip announce strategic partnership
- Empower Semiconductor Secures Over $140M in Series D Financing
- Siemens unveils groundbreaking Tessent AnalogTest software for automated analog circuit test generation
- Euclyd Unveils CRAFTWERK: The World’s Most Power-Efficient Exascale Token Factory for Agentic AI