Updated HBM Standard Geared for HPC, Networking
By Gary Hilson
EETimes, January 18, 2019
TORONTO — High Bandwidth Memory (HBM), like many other memory technologies, is being adopted for emerging use cases that didn’t exist at its inception because of specific characteristics such performance, capacity and power consumption. But it won’t be long before there’s pressure to improve upon them as adoption in newer scenarios takes off.
The Jedec Solid State Technology Association’s most recent update to the JESD235 HBM DRAM standard focuses on meeting the needs of applications in which peak bandwidth, bandwidth per watt, and capacity per area are critical metrics. Such applications include high-performance graphics, network and client applications, and high-performance computing.
To read the full article, click here
Related Semiconductor IP
- HBM Memory Controller
- HBM 4 Verification IP
- Verification IP for HBM
- TSMC CLN16FFGL+ HBM PHY IP
- Simulation VIP for HBM
Related News
- JEDEC Publishes HBM3 Update to High Bandwidth Memory (HBM) Standard
- JEDEC® Releases Updated LPDDR5/5X SPD Standard with Enhanced Mode‑Switching Support
- Avery Design Systems Offers Comprehensive Verification Support for the New HBM3 Interface Standard
- JEDEC Approaches Finalization of HBM4 Standard, Eyes Future Innovations
Latest News
- AiM Future Partners with Metsakuur Company to Commercialize NPU-Integrated Hardware
- ESD Alliance Reports Electronic System Design Industry Posts $5.5 Billion in Revenue in Q4 2025
- Omnitrx introduces Omni500 Ethernet Evaluation Platform, Built on Comcores Expertise
- Three Misconceptions About the $402B Semiconductor Foundry Industry
- TSMC March 2026 Revenue Report