UltraSoC announces industry-first "debug over USB" capability for complex SoCs
CAMBRIDGE, United Kingdom --April 21, 2015 -- UltraSoC, the pioneering provider of advanced debugging and analytic technology for embedded systems, today announces the availability of USB-based debugging capabilities within its flagship UltraDebug® product. This unique, patented technology allows a single high-speed chip interface – in this case USB 2.0 – to be used simultaneously for both system communication and for analytics applications such as debugging. Future developments will support other standard interfaces, such as Ethernet or PCIe.
UltraDebug helps engineers to understand the complex interactions between software and hardware in today’s silicon chips, which frequently boast several billion transistors running tens of thousands of lines of software code. Adding dedicated analytics circuitry to the chip dramatically simplifies the process of debugging – a process which today commonly consumes up to half of the total development time of a large SoC.
Traditionally, designers have relied on debug-specific interfaces – typically JTAG – to “look in” to their chips and analyze their behavior. UltraDebug allows this to be done via an external interface – in this case USB – that is already an intrinsic part of the device’s design. The approach brings many benefits: it is not necessary to provide dedicated I/O pins on the device for debugging; data transfer can be accomplished much more quickly; but perhaps most importantly, the interface remains accessible even once the chip has been assembled into an end product and shipped to the customer. This allows system designers to analyze problems and fine-tune the performance of a product such as a smartphone or a hard disk drive throughout its useful lifetime.
UltraDebug is delivered as silicon IP for integration into the chip design. It provides a holistic, configurable analytics solution that is compatible with IP and processor blocks from any vendor – and is particularly powerful when used in heterogenous systems that include IP from multiple sources. The new USB connectivity feature is backed with advanced security features such as challenge/response capability, cryptographic protection and the ability to completely disable the debug facility, allowing OEMs to deploy products that integrate UltraDebug features with complete confidence.
“We’re now able to offer levels of connectivity that befit the advanced features of UltraDebug,” said Rupert Baines, UltraSoC CEO. “And USB is just the beginning. In a world of 50 billion connected devices, being able to remotely optimize an embedded system is a very powerful capability. We can apply this technology via any communications interface: if your SoC has Ethernet, you can use that for debug; if it’s PCIe, that’s possible too. We’ll be saying more about those capabilities soon.”
UltraSoC will be demonstrating UltraDebug with USB 2.0 connectivity at the upcoming 52nd Design Automation Conference (DAC), (Booth #3501, Moscone Center, San Francisco, June 7 – 11, 2015). At the same event, the company has been selected to deliver a paper on “Design for Analytics”, within the Designer/IP track of the conference.
About UltraSoC
UltraSoC is an independent provider of SoC infrastructure that enables rapid development of embedded systems based on advanced SoC devices. The company is headquartered in Cambridge, United Kingdom.
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- MIPI Alliance Enhances its MIPI NIDnT Debug and Test Specification to Enable Debugging over the Latest USB Type-C Connectors
- UltraSoC enables ultra-high-speed closed-chassis analytics and debug over Synopsys USB3
- UltraSoC delivers first Universal Debug IP to PMC-Sierra
- UltraSoC granted patent on USB based debug interface
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack