Toshiba TAEC creates a corporate D&R user group
San Jose, CA - March 17, 2003 - Finding accurate information about IP to help design managers make the right choices is a real challenge and many large companies design groups may have difficulties getting fast, accurate information about what is available worldwide
To address such an issue D&R proposes easy mechanisms for accessing D&R strategic information across a company. Members of a “corporate D&R user group” get an unique simple corporate wide login and password for accessing D&R’s large set of well established and continually updated resource catalogs ranging from silicon IPs to embedded software, design platform and design services. Thus these designers easily become members of the large community of 25 000 D&R registered users.
Via the IP Search/Find Club, D&R helps these members find in a short time the most accurate answer to a design need, and establish a reliable dialog with potential IP providers. Leveraged by its 100.00 page views per month, this service commits to find worldwide the best solution for SOC designers.
In addition D&R provides a weekly IP/SOC News Alert and a quarterly IP/SOC market analysis.
"The up-to-date information about IP cores and IP companies that D&R gathers daily is valuable to anyone whose business depends on IP cores. We set up a private users group with D&R to make this type information instantly available to our design engineers and business people to support them in closing deals and delivering ASICs. This also supports our goal of propagating the IP re-use culture within our company," said Richard Tobias, Vice President of the ASIC and Foundry Business Unit at TAEC.
"We are glad to leverage the huge effort that D&R provides in updating daily all the SoC resources available in the market. This is another way for helping the SoC business" said Gabriele Saucier chair of the board of D&R.
If D&R is well known for its programs dedicated to IP providers D&R is less known for its user group program granting a valuable set of privileges to large IP consumers.
Please contact D&R to learn more about its user program.
About Design And Reuse
Design and Reuse is the leading web portal for IP and SoC exchange, and the first worldwide provider of intranet/internet XML-based IP reuse and IP supply chain design software called IP/SoC Manager Series. Founded in September 1997 in Grenoble, France, D&R now has operations that extend to Europe, North America and Asia. For more information on Design and Reuse, please visit the website at www.design-reuse.com or send an email to info@design-reuse.com . Telephone (headquarters): +33-4-76706487; Fax: +33-4-76706453.
About Toshiba TAEC
Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes semiconductors, flash memory-based storage solutions, optical communication devices, displays and rechargeable batteries for the computing, wireless, networking, automotive and digital consumer markets.
TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba, the second largest semiconductor company worldwide in terms of global sales for the year 2001 according to Gartner/Dataquest’s Worldwide Semiconductor Market Share Ranking. Toshiba is a world leader in high-technology products with more than 300 major subsidiaries and affiliates worldwide. For additional company and product information, please visit TAEC’s website at chips.toshiba.com. For technical inquiries, please e-mail Tech.Questions@taec.toshiba.com.
D&R Contact:
Gabriele Saucier
saucier@design-reuse.com
+33 476 70 64 87
TAEC Contact:
Deborah Chalmers
Toshiba America Electronic Components, Inc.
(408) 526-2454
deborah.chalmers@taec.toshiba.com
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- Imagination launches IMG CXM, the smallest GPU to bring effortless user interfaces into homes
- NY CREATES and Fraunhofer Institute Announce Joint Development Agreement to Advance Memory Devices at the 300mm Wafer Scale
- Accellera standards group creates designers forum <!-- verification -->
- ASIC designer creates design management tool
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack