Accellera standards group creates designers forum <!-- verification -->
Accellera standards group creates designers forum
By Michael Santarini, EE Times
January 10, 2002 (12:57 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020110S0058
SAN MATEO, Calif. EDA standards organization Accellera has launched a forum to let design tool users identify, participate in and drive future industry standards. Gabe Moretti, former chairman of VHDL International, which merged with Open Verilog International to form Accellera, is the first chairman of the effort, dubbed Accellera Designer Forum (ADF). "Accellera is largely a vendor-staffed organization and what it was missing was greater user participation," said Moretti. "ADF will give users the opportunity to do two things: discuss current issues in EDA and be generators of the requirements for new EDA standards." Moretti said the organization will examine such areas as system-level design, physical synthesis, place and route and design constraints use and management. It will also look at issues with Verilog and VHDL. Moretti said that VHDL International and OVI e ach had its own users groups like ADF but that Accellera had been lagging behind in user input until now. "We sent out a mailing to our users groups and we have received great response," said Moretti. "We received many responses asking what took us so long to get users involved in the organization. It is very encouraging." Moretti said ADF plans to hold its next meeting at HDLCon in San Jose, Calif., March 11 and 12. At the meeting the organization hopes to solidify a charter and organizational structure. ADF membership is free and renewable annually. Interested parties can sign up and get more information about the organization at http://www.eda.org/adf. Moretti, who is EDA editor of EDN magazine, said he will remain chairman of ADF through its launch, after which members will vote to fill the post.
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- VIP for Compute Express Link (CXL)
- HBM4 Controller IP
Related News
- EDA Standards Organizations Accellera and The SPIRIT Consortium Announce Plans to Merge
- Standards Organizations Accellera and The SPIRIT Consortium Complete Merger
- Accellera and the IEEE Standards Association Report on Popularity of Intellectual Property (IP) Standard
- Accellera Systems Initiative Acquires Open Core Protocol Standard and Infrastructure to Strengthen Interoperability in Electronic Standards Development
Latest News
- Quintauris Demonstrates RISC-V Innovation in Automotive at CES
- UMC Reports Sales for December 2025
- Tenstorrent unveiled its first-generation compact AI accelerator device designed in partnership with Razer™ today at CES 2026
- Marvell to Acquire XConn Technologies, Expanding Leadership in AI Data Center Connectivity
- Creonic Releases Updated SDA OCT IP Core Supporting OCT 4.0 and Enhanced Synchronization