STMicroelectronics selects Cadence's Virtual Component Co-Design (VCC) <!-- verification -->
STMicroelectronics selects Cadence
By David Larner, Embedded Systems
November 19, 2001 (4:50 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011119S0002
STMicroelectronics has announced that it has selected Cadence's Virtual Component Co-Design (VCC) for both its Automotive and Digital Consumer platform system-level design methodology and design flow. STMicroelectronics' Audio & Automotive Division uses VCC for behavioural modelling and architectural exploration in automotive design flows. For ST's new power train architecture project, VCC addresses those system-level parts of the design flow that significantly influence SoC size and complexity. This includes behavioural modelling and architecture exploration to enable knowledge transfer with internal and external system customers, and design refinement and export to implementation-level co-verification. STMicroelectronics, one of the world's largest semiconductor manufacturers and a leading supplier of system-on-chip (SoC) solutions, was one of the original VCC development partners.
Related Semiconductor IP
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
Related News
- Cadence Accelerates SoC, 3D-IC and Chiplet Design for AI Data Centers, Automotive and Connectivity in Collaboration with Samsung Foundry
- Dolphin integration unveils a new Virtual Component for power metering
- ProximusDA teams with STMicroelectronics to develop next-generation distributed SOC TLM virtual prototypes
- Cadence Introduces EMX Designer, Delivering More Than 10X Increased Performance for On-Chip Passive Component Synthesis
Latest News
- True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference
- Launch of BrainChip Developer Hub Accelerates Event-Based AI Innovation on Akida™ Platform with Release of MetaTF 2.13
- Agnisys Ignites DAC 2025 with IDesignSpec Suite v9, IDS-FPGA Launch, AI² and IDS-Integrate Enhancements.
- CAST Launches Multi-Channel DMA IP Core Ideal for Streaming Applications
- ZeroRISC Gets $10 Million Funding, Says Open-Source Silicon Security ‘Inevitable’