Standardization nears for next-generation Verilog <!-- verification -->

Standardization nears for next-generation Verilog
By Richard Goering, EE Times
November 15, 2001 (7:09 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011115S0006

SAN JOSE, Calif. - Plans for the next generation of Verilog are unfolding at this week's EDA Front-to-Back Conference, as the Accellera standards organization announces the initial completion of a Verilog extension specification. Many of the proposed enhancements are based on Co-Design Automation Inc.'s Superlog language and Verplex Systems Inc.'s Open Verification Library (OVL).

The "third generation" of Verilog, currently called System Verilog, will permit higher levels of abstraction, said Accellera chairman Dennis Brophy. System Verilog is on a fast track to standardization, with a fully approved Accellera standard expected by the Design Automation Conference next June, he said.

This week Accellera is announcing that its HDL+ Technical Committee has accepted technology donations from Co-Design Automation and Verplex that will be fed into System Verilog. The committee also wants to enhance interface specifications, and add a new construct for assertions. The net result will be a language with even more support for high-level modeling than Verilog 2001, which added a number of behavioral extensions to the language earlier this year.

"We're adding constructs that might look like C to a lot of people," said Brophy. "We're adding significant features Verilog users haven't had in terms of signal abstractions, and we're introducing record structures into the language. The interface definition will allow for signal communications between blocks at a much higher abstraction level."

Subset contributed

Key to providing these capabilities is the Extended Synthesizable Subset (ESS) of the proprietary Superlog language. The ESS subset, not all of Superlog, is what Co-Design Automation has donated to Accellera. "It's one of the catalysts," said Brophy. "It's a major contribution that has sparked excitement in the industry."

But that doesn't mean Verilog will turn into Superlog, or that there aren't other significant technology contributions to System Verilog. Verplex' OVL, Brophy said, will provide a standard library of Verilog assertions that can be used for verification. And aside from vendor technology contributions, the HDL+ committee is bringing its own ideas to the table, Brophy said.

Dave Kelf, vice president of marketing at Co-Design Automation, said that Superlog ESS includes all of Verilog and Verilog 2001, plus features targeted at abstract synthesis and hardware design. "There's a large portion of the C language in there, such as structures and types," he said. "There are communication facilities and state machine representations."

But there's much in Superlog that's not part of the donated subset, including high-level constructs for architectural design, and verification features including test generation and temporal logic. "Superlog will be a superset of System Verilog," Kelf said. "But what we ultimately want to do is to donate other parts of Superlog until the whole language is opened up."

Many chip designers who are skeptical of C/C++ hardware design have warmed to Superlog, because the language is a superset of Verilog that doesn't force an immediate methodology change. To date, however, there's been relatively little commercial EDA tool support for Superlog.

OVL, meanwhile, will be used for a Verilog assertion library proposal. "We want to make sure assertions are written as efficiently as possible for third-generation Verilog, or available in terms of documented source, so that implementations don't necessarily have to use the Verilog code that is supplied to define them," Brophy said.

Separate from that effort, the HDL+ committee has defined requirements for a Verilog facility that will allow the "free-form expression" of assertions, Brophy said. "The technical discourse has just started, and the group is debating the scope and depth of what it should encompass."

Brophy said the HDL+ committee has a "dotted-line relationship" with the Ve rilog Formal Verification committee, which is looking to standardize a formal assertion language that lives outside of Verilog. That committee is reviewing candidates from Intel, IBM, Motorola and Verisity, and is expected to narrow the field of contenders to two within the next few weeks.