A dynamic adaptation of libraries to performance with Dolphin Integration's mixing of standard cells stems

Meylan, France – October 01, 2010. Dolphin Integration opens-up a new approach for optimizing Performance, Power and Area of any logic block through the mixing of library stems with optimal adaptation at "logic path level".

Mixing VTs within a logic block may be an illusory method to tune the optimization of logic block.

- So how should Designers proceed to optimize Performance, Power, and Area while satisfying a speed constraint?

With traditional non-mixable cell libraries, optimization can only be performed at the "logic block level" and library selection is restricted by the speed constraint of few cells on a critical path. To gain flexibility on Performance, Power and Area, Soc Designers only have the possibility to change the library and to select one with a different number of tracks (either 7, 9, 10, 12…).

With SESAME mixable Standard Cell stems, each path of the logic block can be optimized either for Performance, Power or Area. Indeed, when the Density Optimized HD-BTF stem does not reach the speed constraint of a path, the synthesizer shall automatically use speed-optimized cells of the HS-BTF stem. Such mixing capability results in the ultimate flexibility, without any added complexity for Designers as it is handled automatically by any EDA solution.

These two mixable SESAME Standard Cell stems are first released for the 130 nm technological process, soon to be followed by more advanced process nodes.

Please follow the link below to get access to the key benefits and features of our mixable stems, SESAME HD-BTF and HS-BTF

http://www.dolphin.fr/flip/sesame/013/sesame_013_products.html

You can also have a look at the brochure to discover more about SESAME stem mixing capability:

http://www.design-reuse.com/sip/view.php?id=24764

About Dolphin Integration

Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control.

For more information about Dolphin, visit: www.dolphin.fr/sesame