Silistix Hires Katherman as VP of Sales

Thomas Katherman to Manage Worldwide Sales for Self-Timed On-Chip Interconnect Company

SAN JOSE, CA -- August 18, 2006 -- Silistix, a provider of EDA tools for on-chip communications solutions, today introduced Thomas Katherman as the company's vice president of worldwide sales. In this position, Katherman will provide Silistix with sales and marketing expertise to generate greater awareness and accelerate customer adoption of the company's CHAINworks™ tool suite for the design and synthesis of self-timed interconnect technology for system-on-a-chip (SoC) development.

"We are very pleased to have Tom join Silistix as VP of sales," said David Fritz, Silistix CEO. "Tom's years of experience with several of the world's best known semiconductor and silicon IP companies will play an integral part in expanding and managing sales efforts for Silistix in the U.S., Asia and Europe."

A veteran of the semiconductor industry, Tom has over 25 years of senior-level sales and marketing management experience at world-class intellectual property and semiconductor manufacturing companies. Tom was instrumental in establishing the North American Sales channel for UPEK, the world leader in Biometric Fingerprint solutions. Tom also held key sales positions at ARC International, Mitsubishi Electronics America, NEC America and Fairchild Semiconductor.

"I am glad to be part of the Silistix team with its very talented managerial and technical staff," said Katherman. "Today's SoCs are becoming increasingly more complex, with power usage and design time emerging as critically important issues. Silistix's self-timed interconnect, generated by the company's CHAINworks tool suite, is emerging as the best solution for communicating between a chip's intellectual-property cores."

About CHAINworks

System-on-a-Chip complexity has accelerated to the point that the on-chip interconnection of functional blocks by conventional bus technology cannot meet design requirements. Achieving satisfactory communication among multiple clock domains connected by long, slow wires is the most significant SoC design challenge facing designers today. Silistix's CHAINworks technology provides a unique and compelling solution to the complexity problem in a manner analogous to that used by telephone systems as they migrated from circuit-switched to packet-switched communication, revolutionizing the industry in the process. Similarly, Silistix's solution relegates the 'Timing Closure' issue to a much simpler class of problem, and reduces on-chip congestion and overall power consumption.

About Silistix

Silistix is a venture-funded spin-out of the University of Manchester, UK, with backing from Intel Capital. The company's focus is on the development and deployment of EDA tools for the design and synthesis of self-timed CHAIN technology for complex system-on-a-chip (SoC) communication. The company has offices in Manchester, England, San Jose, California, and Tokyo, Japan. For more information call 408-573-6104 or visit www.silistix.com.