SEGGER introduces streaming trace probe for SiFive RISC-V cores
October 25, 2022 -- SEGGER’s J-Trace PRO with streaming trace, Live Code Profiling, and Live Code Coverage now supports all E-Series SiFive RISC-V cores with the BTM trace module.
J-Trace PRO RISC-V, with its SuperSpeed USB 3.0 interface, enables continuous streaming trace via USB. This allows the processing of data from a target device in real time, giving users a deep insight into the application program. Streaming in real time allows for data capture over long periods of time with no limit set on the amount of trace data. This is ideal for code optimization and especially for finding infrequent, hard-to-reproduce bugs.
"Streaming trace is the ultimate key technology in code optimization," says Ivo Geilenbruegge, Managing Director of SEGGER. "Some of our most demanding customers, including SEGGER’s own in-house engineers, use the J-Trace PRO for code optimization and verification. We are delighted that we can also make this experience available to developers working with SiFive RISC-V cores."
J-Trace PRO enables Live Code Profiling by detailing which instructions have been executed how often. This allows users to address runtime hotspots and to identify opportunities to optimize them. These profiles can later be exported using a tool like, for example, SEGGER's Ozone debugger, for documentation and analysis. In addition, J-Trace PRO’s Live Code Coverage lets engineers see code coverage at a glance, showing which instructions have or have not been executed. Code coverage is important for test verification. Hence, running the code coverage analysis in parallel with a test suite clearly shows whether all parts of the application are run through the test, which is a key element of functional tests.
J-Trace PRO is the top product of the SEGGER family of debug and trace probes. In addition to its signature streaming and real-time features, it also includes all the features of J-Link, such as high-performance flashloaders, up to 4 MB/s download speed, and an unlimited number of breakpoints in the flash memory of MCUs.
For more information on J-Trace PRO RISC-V, please visit:
https://www.segger.com/products/debug-probes/j-trace/models/j-trace-pro-risc-v/
Related Semiconductor IP
- MIPI I3C Master RISC-V based subsystem
- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
- RISC-V CPU IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
Related News
- Ashling Microsystems Announces New High Performance Debug and Trace Probe for ARM devices
- ARM Announces Debug Probe for High-Speed Serial Trace
- SEGGER Adds Support for SiFive's Coreplex IP to Its Industry Leading J-Link Debug Probe
- SiFive Announces Key Enablement Of Trace And Debug
Latest News
- Will RISC-V reduce auto MCU’s future risk?
- Frontgrade Gaisler Launches New GRAIN Line and Wins SNSA Contract to Commercialize First Energy-Efficient Neuromorphic AI for Space Applications
- Continuous-Variable Quantum Key Distribution (CV-QKD) system demonstration
- Latest intoPIX JPEG XS Codec Powers FOR-A’s FA-1616 for Efficient IP Production at NAB 2025
- VeriSilicon Launches ISP9000: The Next-Generation AI-Embedded ISP for Intelligent Vision Applications