SCI Semiconductor raises £2.5m to develop security-enhanced microcontroller based on CHERI

Sheffield, UK. -- May 27, 2025 --  UK start-up SCI Semiconductor has raised £2.5m towards developing its security-enhanced microcontroller based on CHERI, a memory securing framework developed by the University of Cambridge and supported by the UK and US governments.

The investment was from NPIF II – Mercia Equity Finance, which is managed by Mercia as part of the Northern Powerhouse Investment Fund II (NPIF II), and also angel investors from the UK and Silicon Valley.

With the funding, the company “now plans to set up a base in Sheffield and recruit a further 20 engineers”, it said. This is on top of its existing team of 20, funded by over £1m in UK government technology development grants.

CHERI, which stands for ‘capability hardware enhanced RISC instructions’, aims to protect against cyber attacks that use software memory misallocation, buffer over flows and other memory hacks.

“Memory safe chips have been shown to prevent 70% of all attacks and would enable organisations to continue using existing software,” claimed SCI CEO Haydn Povey.

The technology moves hardware away from the concept of simple memory address pointers.

Instead, a CHERI-enabled processor expects every address pointer to be accompanied by meta-data that includes permissions, and sandbox upper and lower bounds for the calling function.

SCI is basing its core, called Iceni, on Microsoft’s RV32E CHERIoT-Ibex processor – itself based on a 32bit RISC-V core and the Cambridge research. 32bit addresses in this processor need always to be accompanied by 32bit of meta-data. As it can also run straight RISC-V code, the 64bits of enhanced address are also accompanied by a ‘hidden’ bit.

The first Iceni IC is due to appear this year, said SCI, adding that Google Research has already signed up as a customer.

“The Iceni family have been design for 32-bit embedded applications, with an architecture that supports efficient fine-grained hardware enforced compartmentalisation with safe object-granularity sharing. This delivers complete spatial and temporal memory-safety guarantees that the hardware enforces,” according to SCI. “This combination enables code reuse by restraining the blast radium of attacks, even in third-party code and without requiring complete rewrites. This also ensures that regulations, such as EU product liability directives, become easier to comply with – when most of the reused code can be removed from the end product’s attack surface.”

SCI Semiconductor was founded in 2022 by Povey and Krishna Anne.

Povey founded Secure Thingz which was sold to IAR Systems for £30m in 2018, and his 30 years in the semiconductor industry include 10 years at ARM, while Palo Alto based Anne has held senior roles in tech companies including Secure Thingz, and founded immutable audit trail company DataTrails.

Also in SCI are chip technologists David Chisnall from the University of Cambridge and, Dr David Jackson from the University of Manchester.

NPIFII is a £660m fund for the North of England, which provides loans from £25k to £2m, and equity investment up to £5m, to help SMEs without easy access to finance to start-up, scale-up or stay ahead.

Late last year, SCI tapped out an experimental CHERI IC with LowRISC CIC.