RISC-V Takes a Leap Forward
Event debuts cores, FPGA, AI chips, interconnect
By Rick Merritt, EETimes
December 4, 2018
SAN JOSE, Calif. — RISC-V is open for business, proponents will claim at the first annual summit for the open-source instruction set architecture today. The Silicon Valley event comes at a time when backers say that China is rallying around the architecture with perhaps hundreds of RISC-V SoCs and dozens of cores in the works.
At the event, Western Digital will detail a 32-bit embedded core that it will use in a controller for a consumer solid-state drive set to ship in 2020. It is releasing as open-source both the core and a protocol for a cache-coherent interconnect for RISC-V processors — and it has started work on a 64-bit core.
To read the full article, click here
Related Semiconductor IP
- All-In-One RISC-V NPU
- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
- RISC-V CPU IP
- Data Movement Engine - Best in class multi-core high-performance AI-enabled RISC-V Automotive CPU for ADAS, AVs and SDVs
- 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
Related News
- The Process of FPGA Design Takes Giant Leap Forward With the New Stellar IP Tool from 4DSP
- Thread Group Takes Leap Forward with Availability of First Certified Software Stacks from ARM, NXP, OpenThread and Silicon Labs; Launches Product Certification Program
- A Quantum Leap Forward by Google
- 4i2i, an Aberdeen technology company, takes leap into space after securing deal with NASA
Latest News
- IntoPIX Unveils Enhanced JPEG XS Codec And IPMX / SMPTE ST 2110 Solutions Enabling 4K & 8K Video For OEMs And Developers
- IntoPIX Accelerates Automotive Innovation With TicoRAW & JPEG XS On Lattice Low Power FPGAs
- Qualcomm’s Alphawave Acquisition Targets Data Centers and AI, But What’s Next?
- Tariff Effects and China Subsidies Soften 1Q25 Downturn; Foundry Revenue Decline Narrows to 5.4%
- Alchip Technologies Broadens Global Design Capabilities