RISC-V processor Mr Wolf arrives to solve problems
February 06, 2018 // By Peter Clarke, eeNews
Researchers at ETH Zurich (Swiss Federal Institute of Technology in Zurich) and University of Bologna have received first silicon on their latest PULP-based IoT processor, codenamed Mr. Wolf after the character from the film Pulp Fiction who "solves problems."
PULP is a European parallel ultra-low processor initiative based on the RISC-V open-source processor instruction set.
Mr Wolf is a cluster based processor that features eight 32-bit RI5CY cores implementing the RISC-V ISA, according to Frank Kagan Gurkaynak, director of the microelectronics design center at ETH Zürich, who announced Mr. Wolf's arrival by way of an article on LinkedIn. Besides supporting standard (I)nteger, (C)ompressed, (M)ultiplication and 32-bit (F)loating-point extensions of RISC-V, it also provides our custom e(X)tensions for DSP operations. This processor core is written in System Verilog and is openly available from Github under the SolderPad License .
To read the full article, click here
Related Semiconductor IP
- Custom RISC-V Processor
- 64-Bit 8-stage superscalar RISC-V processor
- 8-stage superscalar RISC-V processor
- Configurable RISC-V processor IP core
- Ultra-Low-Power Deeply Embedded RISC-V Processor
Related News
- Akeana™ exits stealth mode with comprehensive RISC-V processor portfolio, challenging the semiconductor industry status quo
- SiFive Announces New High-performance RISC-V Datacenter Processor for Demanding AI Workloads
- Resiltech and Andes Technology Announce Collaboration to Deliver Advanced STL Solutions for Andes Automotive-Grade RISC-V Processor IP
- The role of RISC-V in the European Processor Initiative - Interview with Roger Espasa
Latest News
- SEMIFIVE Files for Pre-IPO Review on KRX
- Innosilicon Scales LPDDR5X/5/4X/4 and DDR5/4 Combo IPs to 28nm and 22nm, Cementing Its Position as the ‘One Stop’ for Memory Interface Solutions
- Synopsys Completes Acquisition of Ansys
- Zephyr 4.0 Now Available for SCR RISC-V IP
- Lattice Semiconductor and Missing Link Electronics Become Partners to Accelerate FPGA Design Projects