Real Intent describes Verix verification tool

Real Intent describes Verix verification tool
By Richard Goering, EE Times
May 8, 2000 (11:17 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000508S0017

SANTA CLARA, Calif. — Claiming a breakthrough approach to logic verification with its Intent-Driven Verification methodology, startup Real Intent Corp. this week will unveil Verix, its first tool offering. The product reads Verilog RTL code, deciphers the designer's intent and automatically checks for eight types of violations.

Real Intent is a startup founded by two former EDA tool users at Sun Microsystems Inc. EDA veteran Prabhu Goel is chairman of the board of directors, and the company has raised $4 million in venture capital. This week, the company is announcing that Andy Bechtolsheim, a well-known EDA investor, is joining its board of directors.

Verix is the first of two planned product offerings. The second product, Verix-Pro, will allow designers to express intent using a proprietary input format. It will allow a broader range of checks and more accuracy than Verix, but will also require more user interactivity. Verix-Pro is scheduled for an October release, while Verix is scheduled to ship in July.

The idea behind Real Intent's technology is to bridge the gap between the designer's intent and the RTL structure. What's new and different with Verix, said Real Intent chief executive officer Prakash Narain, is the level of automation it brings to RTL verification and the exhaustive analysis it performs for common error conditions.

Eight problems

At the initial release, Verix looks for eight types of problems. These include conflicting assignments, in which a net might have multiple drivers that cause conflicting logic values; range violations, in which vectors might be indexed out of range; and parallel case and full case inconsistencies, which may indicate problems with Synopsys programs.

Also considered are block-enable problems, which can identify enabling conditions that are never met; constant net violations, i n which a net fails to toggle; static X-source problems, in which a net does not have a known driven value; and nonresettable flops, which are flip-flops that don't initialize to a known value.

In addition to those checks, Verix performs an "assignment execution" check that looks for unintended design behavior reflected in variable assignments. Optionally, Verix can produce Verilog test vectors that promise 100 percent state variable and assignment toggle coverage. Those test vectors can be used to create monitors during simulation.

Verix does not require any testbench development, and it's a static product that does not rely on simulation. It promises to verify each check under all possible input conditions, providing fully exhaustive coverage.

"There is virtually no setup and no interaction," Narain said. "During the processing phase, the user need not be involved. It reports violations and you have only to debug the results."

RTL input

Input to Verix is simply synthesizable Verilog RTL. A future release will add VHDL support. Users write a small control script and can disable any unwanted checks. After that, everything runs automatically.

Narain said that Real Intent has so far run blocks as large as 200,000 gates through Verix. At a customer site, he said, Verix processed a design with 2 million to 3 million "gate equivalents" over a 10-day period. The methodology, he said, is incremental and hierarchical.

Output comes in two modes — a textual report and a Java-based GUI. Verix can also output a standard VCD file that can be fed into a Verilog debugging tool. The tool provides the name of the variable involved in the violation, as well as the location in the source code.

"When we report a violation, there is no ambiguity in the result. That makes debugging very easy, as opposed to feedback that says you have a potential problem," Narain said.

Verix pricing begins at $25,000.