Rad3 Communications Inc. announces the appointment of Dr. Stephen Bates to the position of Chief Architect
Calgary, Canada – April 18th , 2010 – RAD3 Communications Inc. (RAD3), a communications intellectual property (IP) company, is pleased to announce that Dr. Stephen Bates has joined the company as Chief Architect. Dr. Bates will be responsible for advanced research and architecture development for Rad3’s growing line of FEC cores.
Dr. Bates is world class expert on the design of LDPC and other FEC decoders. He previously founded Raithlin Semiconductor (www.raithlin.com) to focus on delivering quality algorithm development services and IP to the semiconductor industry. Prior to Raithlin, Dr. Bates was a professor at the University of Alberta’s (UofA’s) department of Electrical and Computer Engineering where he was affiliated with the ICORE High Capacity Digital Communications Lab. In addition, Dr. Bates previously worked for Massana Ltd, a company specializing in the design of Gigabit Ethernet transceivers, which was subsequently acquired by Agere Inc
“The addition of Dr. Bates to Rad3’s management and technical team further strengthens our leading-edge capability in the design and delivery of high performance FEC cores.” said Roger Bertschmann, President RAD3. “As data rates increase to multi-gigabit rates the performance requirement on our FEC cores is ever increasing. Rad3 has achieved great success in licensing its FEC cores into the wired and wireless communications markets and Dr. Bates will bring invaluable experience to Rad3 for further development of these markets.”
About RAD3 Communications Inc.
RAD3 is a leading supplier of communications intellectual property (IP) for new and emerging wired and wireless communication standards. RAD3’s extensive library of IP solutions enables communication companies to rapidly design and build their products using a suite of industry proven IP. For more information, please visit RAD3’s web site: www.rad3comm.com.
Related Semiconductor IP
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
- SHA-256 Secure Hash Algorithm IP Core
- EdDSA Curve25519 signature generation engine
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
Related News
- AMD recruits Apple processor guru as chief chip architect
- Quadric Appoints Former Arm Vice President Steve Roddy as Chief Marketing Officer and Accelerates the Licensing of Its GPNPU Architecture
- Distinguished microprocessor architect, Keith Diefendorff, joins ARC Cores in research role
- Xilinx Design Services Helps Architect Industry's First 10 GBPS Fibre Channel Technology
Latest News
- Analog Bits Demonstrates Real-Time On-Chip Power Sensing and Delivery on TSMC N2P Process at TSMC 2026 Technology Symposiums
- TES offers a High-Frequency Synthesizer and Clock Generator IP for X-FAB XT018 - 0.18µm BCD-on-SOI technology
- Faraday Delivers IP Solutions to Enable Endpoint AI Based on UMC’s 28nm SST eFlash
- AiM Future Partners with Metsakuur Company to Commercialize NPU-Integrated Hardware
- ESD Alliance Reports Electronic System Design Industry Posts $5.5 Billion in Revenue in Q4 2025