QuickLogic Eclipse FPGAs clocked at 600 MHz

QuickLogic Eclipse FPGAs clocked at 600 MHz
By Craig Matsumoto, EE Times
April 19, 2000 (11:33 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000419S0013

SAN MATEO, Calif. — QuickLogic Corp. has unveiled a product family that features what company officials call the fastest internal clock speed of any FPGA, for particular operations that move data without performing logic functions.

The Eclipse line has hit 600 MHz in recent simulations run for QuickLogic (Sunnyvale, Calif.). Externally, connections between Eclipse chips run as fast as 225 MHz.

"We believe it's twice as fast as anything that's out there," said Charles Tralka, the company's director of marketing.

QuickLogic managed some of the speed increase by expanding the logic cells inside the part. "The more you can put into a single logic cell or a single layer of logic, the faster you can run," Tralka said.

QuickLogic added a multiplexer and a register to each logic block and equipped the second register with a "fast path" con nection to the routing array. Using the fast path, data is moved into the register by passing through just one multiplexer.

Thus, each logic cell is designed with a trade-off in mind: extremely high speed for "dumb" movement of data or more typical speeds with logic being performed. QuickLogic's software determines which path to choose depending on the functions being performed.

The need for this kind of operation grew out of customer requests from the image-processing field, where there was interest in replicating the operations being performed on data elsewhere in the chip. That led to an effort to allow data to get into registers without any logic being performed. "Previously, they had to use the whole logic cell to get access to that register," Tralka said.

Reaching 600 MHz for normal operations still isn't possible. "If you wanted to put any kind of logic between those registers, it would slow you down," Tralka said.