QuickCores announces FREE microcontroller CPU netlist library
PLANO, Texas, November 9, 2003
-- QuickCores is pleased to announce that it has posted developmental versions of its Q8051 and Q6805 microcontroller CPU soft cores at its web site for free downloading and may be used without restriction. The Q8051 and Q6805 CPU soft cores should easily synthesize when targeted to Actel ProASIC-PLUS, Xilinx Spartan or QuickLogic Eclipse II FPGAs when using Synplify Lite, or to ALTERA Cyclone when using Quartus II web edition software. The Q8051 CPU is provided in original Verilog RTL source format and features QuickCores real-time monitor architecture. The .zip files contain all the modules necessary for developers to start creating their very own 8051 microcontroller designs in an FPGA, including example top-level designs, simple test fixtures and example C programs for creating stimulus .v files. Also included is a recently enhanced JTAG debug module with 144-channel real-time trace buffer. The 144-channel real-time trace buffer traces, in parallel, a 36-bit time stamp along with the CPU’s Accumulator, B register, Data Pointer, Program Counter, Program Status Word, Stack Pointer, Instruction Register and internal read and write data address and data buses. The trace buffer comprises extra logic which automatically aligns program fetch cycles with decode cycles which helps to eliminate the confusion associated with displaying and interpreting the instruction pipeline in the debugger’s trace window.
Once a breakpoint is encountered, the trace buffer contents are scanned out via the debug module’s JTAG pins. When combined with the QuickCores JTAG-accessible, real-time monitor architecture, the 144-channel trace buffer offers an enhanced visibility into the CPU core during real-time monitoring and debugging operations.
The Q8051 CPU is compatible with both Keil Software C51 C compiler and uVision2 integrated development environment as well as Domain Technologies BoxView real-time debugger software. The Q6805 CPU is compatible with ByteCraft Ltd., Metrowerks, and Cosmic Software 6805 C compilers and Domain Technologies BoxView real-time debugger. Both the Q8051 and Q6805 CPU designs are micro-code free.
QuickCores develops and licenses synthesizable microcontroller IP for embedding in FPGA and ASIC devices. Since its inception in 1996, QuickCores has been focused on adapting the models of popular microcontrollers to include on-chip, real-time monitoring and debug capability. All of QuickCores microcontroller IP is built on a patented real-time monitor and data exchange architecture that enables high speed exchange and monitoring of data between target and host using a JTAG interface. For more information about QuickCores and its products, visit www.quickcores.com .
# # #
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related News
- QuickCores Announces FREE 8051 CPU Soft Core with JTAG Debug
- Toshiba announces availability of free and low-cost development tools for ARM microcontroller families
- NXP to Offer emWin Graphic Library Free with ARM Microcontrollers
- Silvaco and Si2 Release Unique, Free 15nm Open-Source Digital Cell Library
Latest News
- How hardware-assisted verification (HAV) transforms EDA workflows
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology