Visit Quadric at CES to Discover the GPNPU that Solves The Biggest ML Inference Chip Design Challenges
Burlingame, CA – December 11, 2023 – Quadric® today announced that representatives from the company will be at the Consumer Electronics Show (CES) in Las Vegas, January 9-12, 2024. Email meetquadric@quadric.io to set up a meeting to learn how a general-purpose neural processing unit (GPNPU) solves the challenge of needing to artificially partition code between an NPU and a digital signal processor (DSP) and/or central processing unit (CPU).
“Because it’s fully programmable, our GPNPU runs all types of machine learning networks, including classical backbones, vision transformers, and large language models,” stated Steve Roddy, Quadric’s Chief Marketing Officer. “One architecture for ML inference plus pre-and-post processing greatly simplifies SoC hardware design and software programming. Porting new artificial intelligence (AI) and ML code is quick and efficient. No hardware changes are required, which means no silicon re-spins are required.”
Quadric’s processor architecture uniquely combines the best attributes of C++ programmability – the ability to run any ML model – with the performance efficiency of NPU accelerators found in many first-generation SoCs in the market today. But unlike inflexible accelerators that force silicon respins when complex new models such as Llama2 are invented, Chimera cores are fully programmable. Chimera GPNPUs run any model. All of the model – all of the layers. No removal of problematic layers. No partitioning. No forcing the data scientist to convert convolutions to adhere to the limited subset of conv types supported in hardware. Any model, any network, any operator.
About Quadric
Quadric Inc. is the leading licensor of general-purpose neural processor IP (GPNPU) that runs both machine learning inference workloads and classic DSP and control algorithms. Quadric’s unified hardware and software architecture is optimized for on-device ML inference. Learn more at www.quadric.io.
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- DSP Group Unveils DBM10 Low-Power Edge AI/ML SoC with Dedicated Neural Network Inference Processor
- Quadric Appoints Former Arm Vice President Steve Roddy as Chief Marketing Officer and Accelerates the Licensing of Its GPNPU Architecture
- Quadric's New Chimera GPNPU Processor IP Blends NPU and DSP into New Category of Hybrid SoC Processor
- Quadric's DevStudio Speeds Software Development with Industry's First Integrated ML + DSP Cloud-Based Code Development Platform
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack