Quad patterning a possibility at 10nm, says TSMC
Rick Merritt, EETimes
10/30/2012 3:31 PM EDT
SANTA CLARA, Calif. – Quad patterning may be needed for 10-nm process technology if extreme ultraviolet (EUV) lithography is not ready in 2015 or so when Taiwan Semiconductor Manufacturing Co. expects to start early production of the technology.
That’s the view expressed by Jack Sun, chief technologist at TSMC, in a brief interview after his keynote at the ARM TechCon here Tuesday (Oct. 30). Sun said quad patterning--four passes through a lithography stepper using four different masks--was one of several options TSMC is exploring as it works on path finding for the process.
To read the full article, click here
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
Related News
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- TSMC plans 1.6nm process for 2026
- eMemory's Security-Enhanced OTP Qualifies on TSMC N5A Process Specializing in High-Performance Automotive Chips
Latest News
- GlobalFoundries Appoints Matthew Zack as Chief Corporate Development Officer
- VeriSilicon’s NPU IP VIP9000NanoOi-FS has achieved ISO 26262 ASIL B certification
- NVIDIA and Synopsys Announce Strategic Partnership to Revolutionize Engineering and Design
- Presto Engineering Group Acquires Garfield Microelectronics Ltd, Creating Europe’s Most Comprehensive ASIC Design to Production One-Stop-Shop
- Qualitas Semiconductor Demonstrates Live of PCIe Gen 6.0 PHY and UCIe v2.0 Solutions at ICCAD 2025