Quad patterning a possibility at 10nm, says TSMC
Rick Merritt, EETimes
10/30/2012 3:31 PM EDT
SANTA CLARA, Calif. – Quad patterning may be needed for 10-nm process technology if extreme ultraviolet (EUV) lithography is not ready in 2015 or so when Taiwan Semiconductor Manufacturing Co. expects to start early production of the technology.
That’s the view expressed by Jack Sun, chief technologist at TSMC, in a brief interview after his keynote at the ARM TechCon here Tuesday (Oct. 30). Sun said quad patterning--four passes through a lithography stepper using four different masks--was one of several options TSMC is exploring as it works on path finding for the process.
To read the full article, click here
Related Semiconductor IP
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
Related News
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- TSMC plans 1.6nm process for 2026
- eMemory's Security-Enhanced OTP Qualifies on TSMC N5A Process Specializing in High-Performance Automotive Chips
- M31 Launches ONFi5.1 I/O IP on TSMC 5nm Process
Latest News
- PQSecure Collaborates with George Mason University on NIST Lightweight Cryptography Hardware Research
- Omni Design Technologies Advances 200G-Class Co-Packaged Optics IP Portfolio for Next-Generation AI Infrastructure
- Global Annual Semiconductor Sales Increase 25.6% to $791.7 Billion in 2025
- Fabless Startup Aheesa Tapes Out First Indian RISC-V Network SoC
- SmartDV and Mirabilis Design Announce Strategic Collaboration for System-Level Modeling of SmartDV IP