Profile of a traceability tool promising automation in SoC designs
By Majeed Ahmad, EDN
A new tool claims to identify and fix traceability gaps between disparate systems such as requirements, specifications, EDA toolsets, software code, and documentation in system-on-chip (SoC) designs. That allows chip designers to know immediately when a change occurs and its effect on other design artifacts and parts of the system.
Harmony Trace, implemented as an enterprise-level server-based application with a web-based user interface (UI), facilitates complete visibility of requirements traceability throughout the entire SoC design flow and product lifecycle. Moreover, it eases compliance with functional safety and quality standards such as ISO 26262, IEC 61508, ISO 9001, and IATF 16949.
A complex SoC often involves a suite of disparate and disconnected tools. So, when SoC goes through its product lifecycle, design engineers need to manage the whole lifecycle. “That makes it difficult to trace design requirements and artifacts across the SoC lifecycle,” said Mike Demler, senior analyst at The Linley Group. “Harmony Trace mitigates these issues by connecting discrete silos, enabling users to track requirements, implementation, verification and documentation mismatches across existing systems.”
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
- Ultra-low power high dynamic range image sensor
Related News
- Europe takes a major step towards digital autonomy in supercomputing and AI with the launch of DARE project
- InCore Unveils SoC Generator Platform: From Idea to FPGA Validation in Minutes; Demonstrates Silicon Proof of Auto-Generated SoC
- Accellera Announces Standardization Initiative to Address Design Automation and Tool Interoperability for Functional Safety
- Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5/3D Chip Designs
Latest News
- NIST Finalizes ‘Lightweight Cryptography’ Standard to Protect Small Devices
- QuickLogic Appoints Ron Shelton to Board of Directors
- Cadence Accelerates Development of Billion-Gate AI Designs with Innovative Power Analysis Technology Built on NVIDIA
- OIF at ECOC 2025: Eliminating Barriers and Accelerating Innovation Through Industry-Wide Interoperability
- Orthogone Technologies unveils major upgrade to its ULL FPGA Framework to push hardware performance and latency optimization to new heights