Profile of a traceability tool promising automation in SoC designs
By Majeed Ahmad, EDN
A new tool claims to identify and fix traceability gaps between disparate systems such as requirements, specifications, EDA toolsets, software code, and documentation in system-on-chip (SoC) designs. That allows chip designers to know immediately when a change occurs and its effect on other design artifacts and parts of the system.
Harmony Trace, implemented as an enterprise-level server-based application with a web-based user interface (UI), facilitates complete visibility of requirements traceability throughout the entire SoC design flow and product lifecycle. Moreover, it eases compliance with functional safety and quality standards such as ISO 26262, IEC 61508, ISO 9001, and IATF 16949.
A complex SoC often involves a suite of disparate and disconnected tools. So, when SoC goes through its product lifecycle, design engineers need to manage the whole lifecycle. “That makes it difficult to trace design requirements and artifacts across the SoC lifecycle,” said Mike Demler, senior analyst at The Linley Group. “Harmony Trace mitigates these issues by connecting discrete silos, enabling users to track requirements, implementation, verification and documentation mismatches across existing systems.”
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- MIPI SoundWire I3S Peripheral IP
- LPDDR6/5X/5 Controller IP
- Post-Quantum ML-KEM IP Core
- MIPI SoundWire I3S Manager IP
Related News
- InCore Unveils SoC Generator Platform: From Idea to FPGA Validation in Minutes; Demonstrates Silicon Proof of Auto-Generated SoC
- Altera and BigCat Wireless Partner to Accelerate Deployment of Altera’s Open Radio Unit Reference Designs in Wireless Communications Infrastructure
- Accellera Announces Standardization Initiative to Address Design Automation and Tool Interoperability for Functional Safety
- Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5/3D Chip Designs
Latest News
- SEALSQ and IC’Alps Unify Expertise to Deliver Integrated Post-Quantum Cybersecurity and Functional Safety for Autonomous Vehicles
- PUFsecurity’s PUFrt Anchors the Security of Silicon Labs’ SoC to Achieve the Industry’s First PSA Certified Level 4
- The next RISC-V processor frontier: AI
- PQShield joins EU-funded FORTRESS Project: Pioneering Quantum-Safe Secure Boot for Europe’s Digital Future
- PQSecure Achieves NIST CAVP Validation