Process vs. density in DRAMs

Geoff MacGillivray
(07/04/2005 10:00 AM EDT)

The DRAM marketplace is one of the toughest markets in the semiconductor industry because margins are razor thin, even for the most cost-effective manufacturers. Therefore, DRAM makers must continually find ways to reduce cost while meeting market demands for larger memory densities and higher speeds. The most effective method available is to reduce die size through process shrinks and innovative design techniques such as 6F2 cell design.

Examining leading DDR2 DRAM devices manufactured by Micron, Samsung, Infineon and Elpida in terms of both die size and density will also make it possible to infer cost-per-bit information, which ties both of those factors together.

DDR2 devices will be shipping in significant volumes later in 2005 as the transition from DDR occurs. This move is being driven by customer demands for DDR2 performance speed grades of 533, 667 and even 800 Mbits/second at a competitive price. According to Tom Trill, marketing director for Samsung Electronics' DRAM product line, the transition from DDR to DDR2 has picked up over the past couple of months and is looking to reach parity in the third quarter.

Advanced process
Although NAND flash is now the memory technology some vendors are using to push advanced process geometries, DRAM is not far behind. Advanced processes are instrumental to reducing manufacturing costs, and the first company to start production in a new process geometry often has a major advantage in the marketplace. Samsung has won the race to 90 nanometers by being the first vendor to manufacture a 90-nm DDR2 SDRAM. That gives the company a significant die size advantage: Samsung is able to produce a 512-Mbit SDRAM measuring only 71 mm2, or 18 percent smaller than its closest competitor, Infineon Technologies, which offers a 512-Mbit SDRAM measuring 87 mm2 in a 110-nm process.

Even with Samsung's previous generation-the 512-Mbit, 100-nm Rev "B" DDR2 SDRAM-the company entered a process node that is ahead of most of its competitors, many of whom are still developing in 110 nm. However, while Samsung has won the race to 90 nm, both Infineon and Nanya have announced they are moving to 90-nm production.

It will be interesting to see how long it will take Infineon and Nanya to get 90-nm products on the market. Infineon may actually be able to quickly transition to 90-nm technology, since it already made the transition to 193-nm lithography tools when it shifted to 110-nm process technology. A number of companies updated their design lithography tools when entering the 90-nm node; others have not yet switched their design lithography tools and will have to make the adjustment further down the design cycle at a smaller node.

Samsung has stated that transitioning from the 512-Mbit, 100-nm Rev "B" DDR2 SDRAM to the 512-Mbit, 90-nm Rev "C" version was not associated solely with the technology node. Leveraging its experience at the 90-nm node, Samsung has described the process shrink as a rudimentary step. According to Samsung, the challenge was that there were a number of coordinated efforts, including not only the transition from 100 nm to 90 nm but also the one from Rev B to Rev C and the conversion to a 300-mm wafer.

Part of Samsung's latest design was to implement recess channel array transistor (RCAS), a method that reduces transistor area space by implementing a 3-D structural design, increasing the integration level for higher density on a given area. Essentially, this means that instead of having a flat area where the transistor sits, Samsung has created a "hole," providing the transistor with more space to be placed. This is the first device Semiconductor Insights (SI) has identified that takes advantage of RCAS.

Samsung's process leadership with a 90-nm DDR2 device is no fluke. The company has continually been first to many process nodes and is working on shrinking its DDR2 to 73 nm, following in the footsteps of the NAND flash program.

Density considerations
DRAM manufacturers must not only drive down costs with advanced processes, but they also must aggressively design devices for larger capacities. Infineon earned the honor of being the first manufacturer to reach mass production at the 1-Gbit density, with many other vendors, including Micron Technology and Samsung, following closely behind. SI has sourced and is currently analyzing the Micron 1-Gbit DDR2 SDRAM. The added size allows module manufacturers to create 1- or 2-Gbyte DIMMs, which serve to increase computer performance.

However, 1-Gbit parts are not yet ready for mainstream application, since today's computers are limited in the amount of memory they can use. This will be remedied in the near future, as systems are being designed to take advantage of the larger memory densities.

Another method for reducing die size is to implement a more efficient array architecture. The 6F2 cell size array architecture was first implemented by Micron with a 256-Mbit DDR SDRAM with 6F2 cell size in a 110-nm process (MT46V32M8TG-6T), which SI analyzed in 2004. Memory technologies often become bound to a certain cell layout for several generations, with every gain in cell size requiring significant effort to reduce the minimum feature size of the lithography.

Micron is still three years ahead of the industry road map with the first DRAM cell to break free of the constraints of the 8F2 cell. The DRAM cell from Micron achieved an equivalent cell size in 130-nm technology to the 110-nm device laid out in standard 4F x 2F format. That the die sizes were comparable shows that Micron has not paid a die area penalty for the complication of data sensing in a new bit line architecture.

When accepting the 2004 Insight Award for Most Innovative DRAM, Mark Durcan, chief technology officer and vice president of R&D for Micron, commented, "By converting from the commonly used 8F2 to 6F2, we increased potential die per wafer by approximately 20 percent at any given process technology node-reducing our manufacturing cost per bit."

However, since that time, SI has not identified any further DRAM devices that have taken advantage of the array advancement, even from Micron. This is surprising, since a small process node using 6F2 would be able to achieve a very small die size, lowering the cost considerably.

Many factors affect the manufacturing cost for DRAM devices, but a rough comparison on the cost-effectiveness of a design can be found by examining die efficiency in terms of the amount of megabits/mm2. Samsung's 512-Mbit, 90-nm device is significantly ahead (22 percent) of the nearest competition in terms of die efficiency, even when compared with 1-Gbit devices. The 512-Mbit devices are also well-positioned from a density perspective and should experience significant production volumes in the latter half of 2005.

Another interesting point is the die size of the 1-Gbit devices from Micron and Infineon. These devices are approximately twice as large as the 512-Mbit devices. Normally, a larger-density device will have some die area savings over a stacked 512-Mbit die size, since a portion of the device's circuitry does not need to be repeated. However, there is no obvious die area savings in the devices that SI has examined to date. This could be due to the fact that these designs are the first in the 1-Gbit density and have not been optimized for cost yet, since 1-Gbit devices may command some price premium in early production.

Samsung says it has 1-Gbit DDR2 components in engineering samples. It will be interesting to see which process the company uses for those parts. Typically, Samsung starts at a density with a larger process node to work out the design flaws and then ports the design into a smaller geometry. But since it has already proven it can reach 90 nm in a 512-Mbit DDR2, the company may deliver 1-Gbit density at 90 nm in the first generation.

The Samsung device is the only DRAM SI has seen that meets the DDR2 667 speed grade. Other speeds include 533 (Infineon 1 Gbit) and 400 (Micron 1 Gbit).