Imperas Releases Fast Models of PowerPC Processors Through Open Virtual Platforms (OVP) Initiative
Open Source Models Available Now for Free on OVP Website
THAME, United Kingdom, June 8, 2010 – Imperas, which through the Open Virtual Platforms (OVP) initiative (www.OVPworld.org) has become the de facto source for instruction accurate processor modeling and simulation, today announced the release of fast models of PowerPC processors. These models work with the OVP simulator, OVPsim, where they have shown exceptionally fast performance reaching over one thousand million instructions per second (MIPS). The models are free and available as open source from the OVP website.
The addition of the models of the PowerPC cores brings OVP to nearly 50 different models of processor cores, all running at very high speed, and all working with both the OVP and Imperas simulators. All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers to have a development environment available early to accelerate the software development cycle. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP processor models. In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms, such as OS and CPU-aware tracing, profiling code analysis, and multicore debug.
“The Power Architecture is an important embedded processor family,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. “Users have been asking for fast models of the PowerPC processor cores, and we’re now able to deliver these models, open source and free, through Open Virtual Platforms. This is just a continuation of the momentum in the OVP initiative.”
About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website. Detailed quotations regarding OVP are available from http://www.ovpworld.org/newsblog/?p=42.
Fast Instruction accurate models are available from the OVP website for MIPS, ARM, Virage ARC, NEC v850, Power Architecture, OpenCores, SPARC and other processor families.
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- Reference Virtual Platform of ARM Model Running Linux Under SystemC/TLM-2.0 Released by Open Virtual Platforms (OVP)
- Xilinx MicroBlaze Model Provided by Imperas and OVP
- Fast Processor Models of #ARM Cores Released by Imperas with Changes to OVP ARM Core Model Licensing Terms
- Applied Microsystems Announces PowerTAP Support For IBM PowerPC 405CR Embedded Processor Systems
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack