Aldec Announces Phase-Based Linting Methodology
HENDERSON, Nev. -- August 09, 2010 -- Aldec Incorporated, a leader in RTL Simulation and Electronic Design Automation (EDA), announces ALINT™ 2010.06. The release introduces a new methodology, phase-based linting (PBL), which provides structured and prioritized phases for the analysis of HDL design issues, significantly improving development productivity and overall efficiency.
Traditional design rule checking applications analyze HDL designs against a set of hundreds of rules, leaving engineers to manage thousands of error messages from one linting session. ALINT 2010.06 provides structured and prioritized predefined flows, minimizing the number of linting iterations and error messages at each phase, and ultimately eliminating more design issues incrementally at each phase. Default phases may be modified or customized by engineers for adherence to corporate design policies or conducting targeted design rule checks.
ALINT 2010.06 is a design rule checking software solution that supports STARC (Semiconductor Technology Academic Research Center), RMM (Reuse Methodology Manual) and DO-254 “best practice” design rules that define a methodology for efficient reuse and verification of System-On-A-Chip (SoC), ASIC and large FPGAs. ALINT checks VHDL, Verilog® and mixed-language designs for structural, coding and consistency issues prior to simulation and synthesis, which can significantly reduce verification time of complex FPGA and ASIC designs. For a complete description of all product enhancements, review the What's New in ALINT 2010.06 video presentation.
Availability
ALINT 2010.06 is available today and sold directly from Aldec and its authorized worldwide distributors. The product offers support for STARC, RMM, DO-254 and Aldec design rule plug-ins, which are sold separately. For more product information or to download a free evaluation copy, visit www.aldec.com.
About Aldec
Aldec Incorporated is an industry leader in Electronic Design Verification and offers a patented technology suite, including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.
Related Semiconductor IP
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
- I2C and SPI Master/Slave Controller
- AHB/AXI4-Lite to AXI4-Stream Bridge
Related News
- The European Space Agency and Prosilog collaborate to implement a new system level design methodology
- UMC Introduces Breakthrough RFCMOS Design Methodology
- ARM And Synopsys to Deliver Industry’s First Reference Verification Methodology Based on SystemVerilog
- Magma and ARM Release Reference Methodology for RTL-to-GDSII Implementation of ARM9E(TM) Family
Latest News
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- The world’s first open source security chip hits production with Google
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing