Nurlogic moves libraries to IBM 130-nm foundry process
Nurlogic moves libraries to IBM 130-nm foundry process
By Semiconductor Business News
July 30, 2002 (11:23 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020729S0021
SAN DIEGO, Calif. -- NurLogic Design Inc., a developer of library components, has agreed to support foundry customers using IBM's 130-nanometer process technology with standard cell and I/O library components. The company said it has physically and electrically optimized each library component to IBM's process, which is intended for use by system-on-chip (SoC) designers. "We've worked with NurLogic through several generations of our foundry technology because of their established customer base and wealth of IP," said Mike Concannon, vice president of foundry manufacturing services for IBM Microelectronics in a statement. Under the agreement, IBM customers have access to NurLogic's standard cell components and I/O library pad cells. In addition, NurLogic will supply customers directly with the libraries and provide technical support.
Related Semiconductor IP
- Specialized Video Processing NPU IP for SR, NR, Demosaic, AI ISP, Object Detection, Semantic Segmentation
- Ultra-Low-Power Temperature/Voltage Monitor
- Multi-channel Ultra Ethernet TSS Transform Engine
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
Related News
- SkyWater Announces Availability of Cadence Open-Source PDK and Reference Design for SkyWater's 130 nm Process
- NurLogic Further Expands Intellectual Property Offering With Standard Cell and I/O Libraries Utilizing TSMC's Advanced 0.13-Micron Process
- Silicon Wave Selects NurLogic IP for Bluetooth Development; NurLogic Develops Advanced Silicon-on-Insulator Libraries and Memories
- Analyst: McAfee buy moves Intel toward IBM model
Latest News
- GUC Announces Tape-out of UCIe 64G IP on TSMC N3P Technology
- Caspia Launches New RTL Security Analyzer Enabling Agentic Silicon Security Verification
- Europe’s stealth leading-edge process technology
- Combined CapEx of Top Eight CSPs to Exceed $710 Billion in 2026; Google Leads ASIC Deployment with TPUs
- UMC Announces Key Changes in Executive Leadership