NurLogic Implements 4.8GHz Phase Locked Loop Into AMD's Eighth-Generation Processors

SAN DIEGO – June 10, 2002 – NurLogic Design, Inc., a developer of high bandwidth connectivity solutions, today announced the successful implementation of their high-performance Phase Locked Loop (PLL) [analog intellectual property (IP)] into the AMD Opteron™ and eighth-generation AMD Athlon™ processors.  NurLogic and AMD announced the initial agreement in June 2001.

NurLogic delivered an advanced 0.13-micron Silicon on Insulator (SOI) PLL to AMD’s exacting standards for their forthcoming microprocessor family, offering the added benefit of increased performance. The two companies worked closely together during the last several months to design, validate and test this advanced analog solution.

The design challenges to create a PLL such as this are extensive. As CPU frequencies increase to multiple Gigahertz, PLLs must be designed with the lowest possible jitter. Additionally, a process optimized for high-speed digital logic makes it difficult to achieve optimal analog performance. As part of a solution to address these issues, NurLogic developed an innovative PLL architecture to overcome these difficulties. On-chip regulators compensated for the noise environment of large digital devices.  When processing was complete, NurLogic and AMD’s engineering teams worked together to validate a first silicon success.

“We are extremely proud of our eighth-generation processor design, and extremely pleased to have a vendor like NurLogic that we can count on to deliver,” said Bruce Gieseke, Senior AMD Fellow, Computation Products Group.  “Not only did NurLogic work diligently with us throughout the design and validation phases, they designed a PLL that exceeded our expectations.”

NurLogic’s extensive analog expertise was an important component in addressing AMD’s unique PLL requirements. NurLogic’s advanced patent-pending architecture enables optimal operating performance with minimal jitter. NurLogic offers a full line of high performance PLLs ranging from 266 MHz to 4.8 GHz.

“The design of PLLs that are to be deployed in a hostile mixed-signal environment is not for the faint of heart, but NurLogic has mastered the art,” said Thomas H. Lee, professor of Electrical Engineering at Stanford University. “Time and again, NurLogic has proven their ability to innovate brilliant solutions to exceptionally difficult problems, rising to the challenges posed by scaling trends that are highly unfavorable to analog performance. The thoroughness with which NurLogic approaches the issue of sensitivity to process variation has ensured consistent first-silicon success. This is the "A team" of PLL designers!”

According to Michael Brunolli, chief technical officer for NurLogic Design, Inc., “Our goal is to provide great technology and customer satisfaction. We’re glad that we were able to help AMD at such a critical time. This truly is a revolutionary architecture for the PLL. The successful implementation of our PLL into AMD’s microprocessor is a testament to the cooperation of the two companies and their combined skill and experience. We look forward to a long relationship with AMD.”

NurLogic’s Industry Leading PLL Analog IP
NurLogic Design, Inc. is leading the industry in the development of high-end PLLs that support today’s communication, graphics, and microprocessor requirements for the fastest data transfer rates, highest frequencies, and increased bandwidth with low jitter.  Advanced PLL technology is becoming a key design element to manage system clocking and achieve the highest system performance.  NurLogic’s full line of high performance PLLs, ranging from 266 MHz to 4.8 GHz, are available immediately off-the-shelf.

About AMD’s Eighth-Generation Processor Family
AMD’s eighth-generation processor core is planned to mark the introduction of the industry’s first x86-64 technology implementation. This technology is planned to preserve companies’ investments in 32-bit applications, while allowing a seamless transition to 64-bit computing, as those companies require. The processors are designed to deliver high-performance solutions for today’s most demanding applications. The processors are designed to be scalable, reliable and compatible, which can result in lower total cost of ownership. Key innovations include an integrated memory controller, which reduces memory bottlenecks, and HyperTransport™ technology, which increases overall performance by removing or reducing I/O bottlenecks, increasing bandwidth and reducing latency.

About AMD
AMD is a global supplier of integrated circuits for the personal and networked computer and communications markets, with manufacturing facilities in the United States, Europe, Japan, and Asia. AMD, a Fortune 500 and Standard & Poor’s 500 company, produces microprocessors, Flash memory devices, and support circuitry for communications and networking applications. Founded in 1969 and based in Sunnyvale, California, AMD had revenues of $3.9 billion in 2001. (NYSE:AMD).

About NurLogic Design, Inc.
NurLogic Design, Inc. provides high-bandwidth connectivity solutions to the networking and communications industries. NurLogic's products encompass customer-specific and industry-standard integrated circuits and semiconductor IP to deliver value-add to its customers. NurLogic products are targeted at CMOS and silicon germanium technologies, and include high-speed connectivity IP, analog and mixed-signal IP, foundation IP, and PMD  ICs. NurLogic was the recipient of the 2001 Most Innovative New Product  Award in a competition sponsored by the University of California-San Diego  CONNECT program and was recently named one of the “Best 30 Small Electronics Companies” by Electronic Business.  Based in San Diego, California, the company has regional sales offices in Massachusetts and Silicon Valley. NurLogic is a privately held corporation.
 

Headquarters: 5580 Morehouse Drive, San Diego, Calif. 92121.
Tel: 1-877-NURLOGIC. On the web at www.nurlogic.com.

NurLogic is a trademark of NurLogic Design, Inc. All other trademarks are the property of their respective owners.