Numem at the Design & Reuse IP SoC Silicon Valley 2024
SUNNYVALE, CA, UNITED STATES, April 24, 2024 -- Numem, the pioneering provider of Memory SOC IPs and Chip/Chiplets, is excited to announce that Numem CEO Jack Guedj will discuss cutting-edge memory solutions at the Design & Reuse IP SoC Silicon Valley 2024 event, which will take place on April 25th, 2024, at the Hyatt Regency Santa Clara, CA. We invite you to join us for this insightful session.
- Date / Time : April 25th / 9:30 am – 10:30 am
- Place : Room B at the Hyatt Regency Santa Clara
- Session : Chiplet Solutions
- Topics : Chiplet-Based Compressed LLC Cache & Memory Expansion IP Solutions
- Link : https://www.design-reuse-embedded.com/ipsocdays/2024/SiliconValley/
Through this event, we will present our state-of-the-art low-power NuRAM Memory (MRAM-Based) and our SmartMem SOC Subsystem, IP Cores and Memory SOC Chiplets. Numem NuRAM's memory is 2-3X smaller in area and 85x - 2000x lower leakage power than SRAM. It is augmented by our SmartMem SOC Subsystem, which includes:
- SmartMem PEP (Performance, Endurance, and Power) Engine: Dramatically improves memory endurance and performance as well as operating power not only for Numem NuRAM but for all persistent memory types (MRAM, ReRAM, PCRAM, etc.) and both embedded and external Flash
- SuperBIST: Fast device bring-up/testing, continuous diagnostics.
- SmartMMC: Simplified memory operation, power/performance optimization.
- Compute/Processing: Enabling 5~10x area reduction or increased density with ZeroPoint technology
About Numem
Numem, headquartered in Sunnyvale, California, is the leading provider of Memory and SOC Subsystem IPs and Chip/Chiplets based on proven foundry MRAM process. Numem’s patented NuRAM technology enables best in class power/performance and reliability with 2.5x smaller area and >85x lower leakage power than traditional SRAM. Numem’s SmartMem technology significantly improves performance and endurance as well as ease-of-use and reliability for high-volume deployment. Numem Chip/Chiplets enable significant power reduction in AI systems from Edge Node to Server applications. Numem SmartMem can be used in conjunction with other memory technologies including MRAM, RRAM, PCRAM or Flash. It has optional and customizable SOC Compute in Memory which enables to further reduce power or increase effective density.
Visit our website at www.numem.com or contact us at info@numem.com.
Related Semiconductor IP
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
Related News
- Arteris Addresses Silicon Design Reuse Challenge with New Magillem Packaging Product for IP Blocks and Chiplets
- Aion Silicon Joins Intel Foundry Accelerator Value Chain Alliance to Design and Deliver Best-in-Class ASIC and SOC Solutions
- 2025 TSMC OIP Ecosystem Forum Highlights Aion Silicon’s Leadership in Advanced SoC Design
- Aion Silicon Expands Barcelona Design Center to Meet Surging Demand for ASIC and SoC Solutions
Latest News
- GUC Monthly Sales Report – March 2026
- Qualitas Semiconductor Licenses 2nm Process-Based MIPI C/D-PHY IP to U.S. Edge AI SoC Company
- Global Semiconductor Sales Increase Substantially in February
- Hardware Root of Trust Essential for AI Chip Integrity
- AI Compute Demand Drives 44% YoY Growth for Top 10 Global Fabless IC Firms in 2025