Nios Soft Core Processor Rides the Performance Curve on Altera's Stratix Device Family

Stratix Device Support for Nios Processor Brings 125 MHz Operation and Expanded Memory Resources

Embedded Processor Forum, San Jose Calif., April 29, 2002 — Altera Corporation (Nasdaq: ALTR) today announced the immediate availability of version 2.1 of the Nios^® soft core embedded processor with full support for Altera's new Stratix^™ programmable logic device (PLD) family. Version 2.1 of the Nios embedded processor is fully optimized to take advantage of the Stratix device family's TriMatrix^™ on-chip memory, high-performance interconnects, and embedded digital signal processing (DSP) blocks.

Running at over 125 MHz, the new version of the Nios soft core embedded processor capitalizes on the Stratix device family's high-speed MultiTrack^™ interconnect to extend its performance advantage over other soft core embedded processors targeting PLDs in designs that include on-chip memory and a UART. Embedded system designers can now take full advantage of Nios' enhanced performance as they continue to push the innovation of network, telecom, mass storage, and other high-bandwidth applications.

"By optimizing the Nios processor for their Stratix devices, Altera makes a strong case for the widespread use of soft core processors in PLDs, especially when compared to its initial release almost two years ago," said Cary D. Snyder, senior analyst with MicroDesign Resources. "The higher performance, additional memory resources, and embedded DSP blocks available with Stratix devices will increase the application space that can use Altera's Nios soft core embedded processor, and strengthen the already compelling reason for embedded designers to consider the use of PLD-based processors."

Since its introduction in 2000, the Nios soft core processor is being used by more than 6,100 engineers around the world and is becoming the de-facto industry standard for soft-core PLD processors. A study released by CMP Media LLC at the San Francisco Embedded Systems Conference in March ranked Nios among the top ten 16-bit processors in use today, and among the top ten 16-bit processors engineers said they planned to use in their next design. In that study, the Nios processor was the only soft core processor listed.

"The Nios processor takes PLD design to an entirely new level," said Michael Bohm, chief scientist for the HDL design division of Mentor Graphics Corporation (Nasdaq: MENT). "The combination of an embedded processor with high-performance PLDs like Stratix devices is the key to addressing a huge assortment of system design issues."

While the MultiTrack interconnect technology gives the Nios processor the edge in performance, designers can implement multiplication operations entirely in hardware by harnessing the multipliers in the Stratix device family's embedded DSP blocks. Using the SOPC Builder development tool in concert with the Quartus^® II design software, this methodology increases the performance of integer multiplication operations over software-only implementations. Software implemented multiplication can take up to 250 clock cycles (32-bit by 32-bit resulting in a 32-bit product). The same multiplication done in a Stratix DSP block takes only one clock cycle.

Nios processor users can also optimize their system data flow using the simultaneous multi-master Avalon^™ bus and increase their data processing abilities by utilizing custom instructions. These features allow designers to easily increase system performance without requiring a higher f_MAX.

With up to 10 Mbits of memory available to Stratix device designers and RAM blocks that run at up to 300 MHz, Nios processor users will benefit from decreased reliance on external memory devices, thus lowering system costs. The abundant high-speed memory resources in Stratix devices combined with the capabilities of the Nios processor is a potent solution for network co-processing tasks such as packet header and payload processing.

"The success of the Nios processor has validated soft CPUs," said Jordan Plofsky, Altera's senior vice president of application business groups. "One of the clear benefits that we are seeing is that soft processors can ride the performance curve of advancing silicon technology. Nios processor users have immediate access to 0.13-micron technology and the advanced silicon features that come with Stratix devices."

The new version of the Nios embedded processor includes the SOPC Builder development tool, version 2.52. With the upgrades made to both the processor and the system development tool, designers can generate a Nios processor design optimized for specific Altera devices. SOPC Builder generates hardware description language (HDL) that specifically utilizes features of the targeted device family. Targeting Stratix devices results in a savings of up to five hundred logic elements (LEs) when compared to other device families. For more information on SOPC Builder, visit http://www.altera.com/sopcbuilder. Also shipping with the Nios processor version 2.1 is the Quartus II Limited Edition software version 2.0 and LeonardoSpectrum^™ software version 2002a.
Pricing and Availability
The Nios embedded processor version 2.1 update is now shipping to all customers with up-to-date Nios processor subscriptions. Purchase of the Excalibur development kit, featuring the Nios embedded processor, entitles customers to one year of free updates. For customers whose first year of free updates has expired, Altera is introducing the Nios subscription renewal. Available today for $495, the subscription renewal extends customer product updates for one year.
About the Nios Embedded Processor
An Excalibur embedded processor solution, the Nios soft core embedded processor is a general-purpose RISC processor that can be combined with user logic and programmed into an Altera PLD. The processor features a 16-bit instruction set and user-selectable 16- or 32-bit data paths, configurable for a wide range of applications. The Nios embedded processor is license and royalty free when used in Altera PLDs and HardCopy^™ devices. For more information, visit http://www.altera.com/nios.
About Stratix Devices
Stratix devices are based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities ranging from 10,570 to 114,140 logic elements LEs and up to 10 Mbits of RAM. Stratix devices offer up to 28 DSP blocks with up to 224 embedded multipliers, optimized for DSP applications that require high data processing. Stratix devices support various differential I/O electrical standards such as the LVDS, LVPECL, PCML, and HyperTransport^™ standards, as well as high-speed interfaces, including the UTOPIA IV, SPI-4 Phase 2, SFI-4, 10G Ethernet XSBI, RapidIO^™, and HyperTransport interfaces. Stratix devices also offer a complete clock management solution with its hierarchical clock structure and up to 12 phase-locked loops. For more information, please visit http://www.altera.com/stratix.
About Altera
Altera Corporation (Nasdaq: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at http://www.altera.com.

Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. LeonardoSpectrum is a trademark of Mentor Graphics Corporation. HyperTransport is a trademark of the HyperTransport Consortium. RapidIO is a trademark of the RapidIO Trade Association. All other product or service names are the property of their respective holders.
 

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