Arithmetic Processing IP Core for MP3 Decoders Feature Smallest Circuit Size and Lowest Power Consumption
July 12, 2010 -- Murata Manufacturing Co., Ltd., in collaboration with Mathematec Corporation, has developed an arithmetic processing IP core for MP3 decoders that uses less than 10% of the power required for conventional general software processing.
With the proliferation of mobile devices with audio music playback features, and other increasingly advanced functions, the challenge is to find ways of reducing power consumption in future designs.
Using Murata's original hardware processing, we have developed an arithmetic processing IP core that will significantly reduce the arithmetic processing load within MP3 decoders. *1
By optimizing circuits with original Murata architecture, used in conjunction with the Spinor® circuit compression technology developed by Mathematec Corporation, we have succeeded in achieving a circuit size and power consumption level that rank among the smallest and lowest ever to have been developed. *2
This product will be made available to customers as a synthesizable soft macrocell. In addition to providing hard macrocells optimized for specific processes, we can also address customer unique requirements.
Features
-
Use less than 10% of the power required for conventional software processing *3
-
Small circuit size of 32000 gates + 76 kbit RAM
-
Low power consumption of 0.35 mW when implemented in IBM9SFLP process
-
Allows for real time decoding of MP3 bit streams at a 6 MHz clock rate
Basic Specifications
Compliant with MP3 (ISO/IEC11172-3, ISO/IEC13818-3) standards
| Clock rate: | less than 20 MHz (real time decoding possible at 6 MHz) |
|---|---|
| Circuit size: | logic circuit – approximately 32000 gates, 76 kbit RAM |
| Power consumption: | 0.35 mW (44.1 kHz 128 kbps Stereo, when implemented in IBM9SFLP process) |
Production
Product available starting July, 2010
Annotations
| *1: | As a rule software or hardware-based implementation of initial MP3 processes (header decoding, Huffman decoding) will be carried out by the customer. Murata's engineering staff will provide technical assistance with these processes upon customer request. |
|---|---|
| *2: | As shown by evaluation results of implementation in the IBM9SFLP process. |
| *3: | Based on company research and observed results, we assume the power consumption of conventional software processing to be approximately 4 mW. |
About Mathematec Corporation
The Mathematec Corporation carries out research and development in circuit reduction technology for system LSI and FPGA, as well as the commercialization of this business area. The company integrates mathematical science and technology to design basic electronic circuits which dramatically improve performance and cost efficiency.
Related Semiconductor IP
- VESA DSC 1.2a Decoder
- BCH Encoder and Decoder IP Core
- DSC 1.2b Decoder
- LDPC Decoder for 5G NR and Wireless
- DVB-S2X Wideband LDPC BCH Decoder
Related News
- CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core Available For Licensing and Implementation from Global IP Core
- DVB-RCS2 Turbo Decoder and Encoder IP Core Available For Integration From Global IP Core
- DVB-T2 Demodulator + Decoder LDPC/ BCH IP Core Available For Immediate Implementation From Global IP Core
- DVB-S2X LDPC/ BCH Encoder and Decoder IP Core Available For Integration From Global IP Core
Latest News
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Arm Announces Appointment of Eric Hayes as Executive Vice President, Operations