Mosis offers IBM 90-nm process on MPW
Peter Clarke, EE Times
(05/09/2006 3:13 PM EDT)
MUNICH, Germany
(05/09/2006 3:13 PM EDT)
MUNICH, Germany
â The Mosis integrated circuit fabrication service has begun offering multi-project wafer (MPW) runs on 90-nanometer process technologies from IBM, according to Paul Double, managing director of EDA Solutions Ltd.
The process is the 9SF process, which comes in three variants, low power digital, standard digital and analog and RF, said Double. The first customer submission deadline is Dec. 4, 2006, according to the Mosis website.
To read the full article, click here
Related Semiconductor IP
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
- SHA-256 Secure Hash Algorithm IP Core
- EdDSA Curve25519 signature generation engine
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
Related News
- Dolphin Integration first to achieve 0.84 pA per bit in SpRAM at the 90 nm uLL embedded flash process
- Dolphin Integration announces the availability of the new generation of SpRAM generator at 90 nm and 55 nm eFlash
- Mikron Licenses Cadence Physical Verification System and QRC Extraction Solutions for 90 nm IC Design Flow
- Dolphin Integration announce the availability of the TSMC sponsored sROMet and DpRAM generators at 90 nm LP eFlash
Latest News
- Analog Bits Demonstrates Real-Time On-Chip Power Sensing and Delivery on TSMC N2P Process at TSMC 2026 Technology Symposiums
- TES offers a High-Frequency Synthesizer and Clock Generator IP for X-FAB XT018 - 0.18µm BCD-on-SOI technology
- Faraday Delivers IP Solutions to Enable Endpoint AI Based on UMC’s 28nm SST eFlash
- AiM Future Partners with Metsakuur Company to Commercialize NPU-Integrated Hardware
- ESD Alliance Reports Electronic System Design Industry Posts $5.5 Billion in Revenue in Q4 2025