Microprocessor consortium to add energy spec

By Spencer Chin, Courtesy of EE Times
Nov 9 2004 (15:02 PM

MANHASSET, N.Y. — In a move to address the growing importance of power and energy efficiency as a selling point for processors, the Embedded Microprocessor Benchmark Consortium (EEMBC) plans to add an energy consumption metric to the performance scores it provides for embedded processors tested against its application-focused benchmarks.

The consortium has formed two working groups to establish methodologies for the energy consumption benchmarks. One group addressing energy measurements for hardware platforms and devices is being headed up by Shay Gal-On of PMC-Sierra.

A second group addressing energy measurements using simulation for intellectual property (IP) processor cores is being headed up by Moshe Sheier of CEVA.

The consortium has also engaged the services of David Kaeli, associate professor in Northeastern University's Department of Electrical and Computer Engineering and director of its Computer Architecture Research Laboratory, to guide its energy benchmark developments.

EEMBC's members have agreed that the energy metric will be an optional component of the performance benchmark scores published for each processor and will take into account the energy consumed by the benchmarked devices while running each of the consortium's application-focused benchmark suites.

Besides providing design engineers with comparable energy consumption information, the new metric will give designers insights into the "cost" of a device's performance in terms of the power budget, by allowing a performance/energy number to be derived using the consolidated performance score in each benchmark suite.

Once the standardized methods are finalized, details of how EEMBC measures energy consumption will be available for download from the group's website.