IP Software Integration Left Out in the Cold
Brian Bailey, Engineering Consultant & EETimes DesignLine contributing editor
EETimes (7/19/2013 11:40 AM EDT)
We are getting close to the end of the series of questions about IP that I asked the industry back in June. But don't fear: I did a whole roundtable on the subject at DAC and will be bringing that to you before long.
Last week I asked about IP theft and protection. One thing that has been happening in the IP market is that the average block size has been getting larger. In the early days of reuse, blocks were fairly small, but today many IP blocks are complete subsystems carrying an extensive amount of software. I asked about the ease with which that software can be integrated. Below are the answers I received
To read the full article, click here
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related News
- New MIPI SDCA Specification Simplifies Audio Software Architecture and Driver Requirements, Optimizing Integration of Audio Devices into Open Host Platforms
- Leader And IntoPIX Boost IP Stream Monitoring With JPEG XS Integration
- Cadence and MathWorks Announce New Integration to Accelerate Data Mining and Analytics
- Xilinx Announces Integration of 56G PAM4 Transceiver Technology into its Virtex UltraScale+ FPGAs
Latest News
- iSTART-TEK Completes FMEDA Analysis to Help Customers Build ISO 26262-Compliant Automotive ICs
- Smarter, Faster, More Personal AI Delivered on Consumer Devices with Arm’s New Lumex CSS Platform, Driving Double-Digit Performance Gains
- Electronics Monitoring Leader proteanTecs Raises $51M in Series D Funding
- Jmem Tek has achieved NIST CAVP certification, with ASCON algorithm implementation, and will be showcased at SEMICON Taiwan.
- Cadence Expands Digital Twin Platform Library with NVIDIA DGX SuperPOD Model to Accelerate AI Data Center Deployment and Operations