IP SoC panel touts multithreading

Mike Santarini
(12/09/2004 11:16 AM EST)  

GRENOBLE, France — The use of multithreading to address power and compute efficiency in embedded SoCs was the predominate topic of a panel here Thursday (Dec. 9) on the closing day of the IP SoC conference.

Panelists Brani Buric, director of product marketing at Virage Logic, AMCC's vice president of marketing Sam Fuller and LSI Logic's European FAE Manager Kai-Uwe Killiches were joined by moderator Tom Petersen, MIPS' marketing director, in a discussion slanted heavily toward MIPS multithreading — essentially software-dominated multiprocessing within one processor.

"I like to think of multithreading as discrete CPUs that are running different tasks," said Petersen. "It's a multiprocessor but not a symmetric multiprocessor. It could be one thread is running Linux and another thread is running an audio decoder."

Virage's Buric argued that as wireless applications have emerged as a powerful market low power design, the fight to conserve battery power has become a key challenge in many embedded SoC design's today.

Buric noted that as design groups put more hardware based functionality controlled by an increasing amount of software on wireless applications, there is an increasing strain on power usage and thus battery life. Buric described a push to develop IP and design blocks at 90 nm with "standby" functions to conserve power and cut leakage. At the 65-nm node, when there is a greater amount of hardware and software functions crammed onto a single die, the ability to shut off certain functions until they are needed will become important.

MIPS' Peterson argued that multithreading increases the efficiency of a given processor and thus cuts the amount of time spent processing.

Audience members noted that multithreaded processing on power-hungry architectures isn't going to displace competing architectures tailored strictly for low power design any time soon. They reasoned that multithreaded cores still require large amounts of power to run large amounts of software in threads efficiently.

Peterson said that with microprocessor companies such as Intel easing off as of late on the drive for greater performance measured through the metrics of MHz and GHz, processing efficiency is becoming a key metric, which plays right into MIPS' multithreading strategy.