Intilop's 10G Full TCP Accelerators with Network Security Features IP Core for Altera/Intel FPGAs qualified by major University and Government clients
Milpitas, CA. -- Mar 30, 2017— Intilop, Inc., a pioneer, most respected and recognized leader in providing Ultra-Low latency and Hyper Performance Complex Networking Protocol Accelerators like Full TCP, UDP, IGMP & other Mega IP Cores, Systems and Solutions since 2009, delivers yet another industry first: a full TCP and UDP Accelerator with Network Security capability which performs functions of firewall and other monitoring functions at full line rate. In addition to full TCP/UDP offloading, this security module performs port filtering, blocking, monitoring and related functions in FPGA hardware thereby relieving CPU from these tasks. They are performed in nanosecond speeds and with ultra-precision and zero jitter. During network security processing, the CPU gets bogged down under high traffic rates, sometimes missing some ‘Events’, can be used for other application functions. So this is a win-win situation for both.
Ultra-fast and precise processing time of around 100 nanoseconds for this module including TCP and UDP with thousands of sessions initially at 10G, sets the bar much higher for speed and performance powered by a 7+ year mature and proven TCP Protocol Compliant architecture. The Security module for their latest 40G TOE on Arria-10 FPGAs is planned for Q3 2017
It was a highly significant achievement to develop this cutting edge technology rich architecture which implements Network Security module coupled with TCP and UDP Accelerators running at Full 10G Line rate on a Stratix V FPGA. The 10G TOE has been in volume production for more than 6 years now and is deployed around the globe. Their 40G TOE & UOE with Secuirty features is planned for Q3 2017.
Working out of the box solutions with Choice of Cores implemented with this security module with 32 through 128 sessions are available now. TOE+Security with 1K, 512 and 256 concurrent TCP/UDP Sessions will be available later this year.
A sample of their TCP and UDP Accelerators can be found also at Altera and Xilinx websites:
- Altera/Intel: https://www.altera.com/products/design-software/embedded-software-developers/opencl/developer-zone/opencl-reference-platforms.html
- Altera/Intel: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/br/br-intellectual-property-brochure.pdf
- Xilinx: http://www.xilinx.com/esp/datacenter/data_center_ip.html
Not only it offers 100 ns latency and wire speed TCP performance with security features, it also offers customization flexibility to network architects to design world-class system-level applications tailored to their specific needs.
The TOE’s architecture is highly scalable, customizable and adaptable without compromising on low latency or performance. Intilop’s product-line solutions are available in flexible FPGA/ASIC/SoC technologies which can easily accommodate diverse set of appliance maker’s technical design specifications.
As a pioneer, Intilop was the first company to deliver a series of Full TCP Offload Engines on FPGAs in 2009. Since then, they have released 7 generation, from 1G to 40G/50G, of TCP and UDP Accelerators. Their sub 100 ns latency MAC+TOE&UOE are considered a ‘Gold Standard’ by the industry experts.
The latency barrier of 100 nanoseconds and throughput of more than 1 G byte/s per port had been set by them since their first 10G Series of TCP engines in 2011.
About Intilop.
Intilop is a developer and pioneer in advanced networking silicon IP and system solutions, custom hardware solutions, SoC/ASIC/FPGA integrator and total system solutions provider for Networking, Network Security, storage and Embedded Systems. They offer silicon proven semiconductor IPs with comprehensive hardware and software solutions.
Website: www.intilop.com
Related Semiconductor IP
- High Speed Ethernet Quad 10G to 100G PCS
- 10G PHY for Differential Buffer, TSMC N7, North/South (vertical) poly orientation
- Multiprotocol 10G PHY, TSMC N7 x2, North/South (vertical) poly orientation
- 10G PHY for PCIe 3.0, TSMC N5 X1, North/South (vertical) poly orientation
- 10G PHY for PCIe 3.0, TSMC 7FF x4, North/South (vertical) poly orientation
Related News
- Intilop presents at Server Design Summit, how their ultra high performance 10G full TCP Offload Technology increases the network bandwidth by up to 6 times
- Intilop delivers on Altera FPGAs, their 7th Gen. industry first, Full TCP, UDP & IGMP Hardware Accelerator System with Dual 10G ports for all Hyper Performance Networking Systems
- Intilop releases Network Security TOE Module for Altera and Xilinx FPGAs for their 10G & 40G Full TCP & UDP Offload Engines
- Another Industry first: Extreme Networking- 1K TCP & UDP Session on intel/Xilinx FPGAs, high availability application performance - 2U Accelerator box with Linux iWARP/RoCE
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers