10G TCP Offload Engine+MAC+PCIe+Host_IF Very-Low Latency (XTOE+PCIe)

Overview

INT 10012 is the only SOC IP Core that implements a full 10G bit TCP Stack in Handcrafted, Ultra-Low Latency and Very High Performance, Innovative, Flexible and Scalable architecture which can also be easily customized for end product differentiation. It provides the lowest latency and highest performance in the industry. No exceptions…..

INT 10012 is the only SOC that integrates 10G TOE + 10 GEMAC + CPU + PCIe/DMA interfaces in the smallest logic footprint. It is highly flexible that is customizable for layer-3, layer 4-7 network infrastructure and network security systems applications. It is recommended for use in, among others, high performance Servers, NICs, SAN/NAS and data center equipment design applications. It provides key IP building blocks for very high performance 10-Giga bit Ethernet ASIC/ASSP/FPGAs.
INT 10012 has built in advanced architectural flexibility that provides capability for enterprises to differentiate their Network security and Network infrastructure appliances from others and customize them for their specific design application.

INT 10012 can process TCP/IP sessions as client/server in mixed session mode for Network equipment and in-line network security appliances, simultaneously, at 10-G-bit rate. This relieves the host CPU from costly TCP/IP software related session setup/tear down, data copying and maintenance tasks thereby delivering 8x to 15x TCP/IP network performance improvement when compared with TCP/IP software.

Key Features

  • Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
  • Provides lowest latency and highest bandwidth (NETWORK PROVEN)
    • Latency through 10 G TOE = less than 200 ns
    • Very-High Throughput, Full Duplex: Receives and Sends sustained large TCP payloads, depending upon remote server/client’s capability
    • Fully Integrated and tested on Altera/Xilinx FPGAs; TOE+MAC+PCIe/DMA+Host_I/F SoC IP bundle

Benefits

  • Accelerates TCP/IP performance by 10-20 times

Block Diagram

10G TCP Offload Engine+MAC+PCIe+Host_IF Very-Low Latency (XTOE+PCIe) Block Diagram

Deliverables

  • Netlist
  • Source(optional)
  • Verilog

Technical Specifications

Availability
Q4, 2007
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Semiconductor IP