Intel backs RISC-V for Nios FPGA processor
By Nick Flaherty, eeNews Europe (October 06, 2021)
Intel has developed a soft IP microcontroller core for its FPGAs using the oipen source RISV-V instruction set
The Nios V processor is the next generation of soft processor for Intel’s Cycline, Stratix and Aria FPGAs based on the open-source RISC-V Instruction Set Architecture. This processor is available in the Intel Quartus Prime Pro Edition Software starting with version 21.3. This follows the 32bit Nios II, launched over a decade ago by Altera in Quartus 8.
To read the full article, click here
Related Semiconductor IP
- Compact Embedded RISC-V Processor
- Highly configurable HW PQC acceleration with RISC-V processor for full CPU offload
- Vector-Capable Embedded RISC-V Processor
- Tiny, Ultra-Low-Power Embedded RISC-V Processor
- Enhanced-Processing Embedded RISC-V Processor
Related News
- Intel Launches Agilex 7 FPGAs with R-Tile, First FPGA with PCIe 5.0 and CXL Capabilities
- Intel Launches Altera, Its New Standalone FPGA Company
- Codasip selected to design a high-end RISC-V processor for the EU-funded DARE project
- 32-bit RISC-V processor based on two-dimensional semiconductors
Latest News
- RISC-V Pivots from Academia to Industrial Heavyweight
- Arteris Technology Deployed More Broadly by NXP to Accelerate Edge AI Leadership
- Avalanche Technology and NHanced Semiconductors Deliver the Industry’s First Truly Space Grade MRAM Boot Solution for RadHard System-in-Package Integration
- Marvell Completes Acquisition of XConn Technologies
- Rambus Announces Departure of Chief Financial Officer