Intel backs RISC-V for Nios FPGA processor
By Nick Flaherty, eeNews Europe (October 06, 2021)
Intel's Nios V soft processor for its FPGAs uses the RISC-V: RV32IA architecture with atomic extensions, 5-stage pipeline and AXI4 interfaces.
Intel has developed a soft IP microcontroller core for its FPGAs using the oipen source RISV-V instruction set
The Nios V processor is the next generation of soft processor for Intel’s Cycline, Stratix and Aria FPGAs based on the open-source RISC-V Instruction Set Architecture. This processor is available in the Intel Quartus Prime Pro Edition Software starting with version 21.3. This follows the 32bit Nios II, launched over a decade ago by Altera in Quartus 8.
To read the full article, click here
Related Semiconductor IP
- Highly configurable HW PQC acceleration with RISC-V processor for full CPU offload
- PQPerform-Inferno + RISC-V processor for enhanced crypto-agility
- Multi-core capable RISC-V processor with vector extensions
- High Performance 64-bit RISC-V Processor
- Custom RISC-V Processor
Related News
- Intel Launches Agilex 7 FPGAs with R-Tile, First FPGA with PCIe 5.0 and CXL Capabilities
- Intel Launches Altera, Its New Standalone FPGA Company
- The role of RISC-V in the European Processor Initiative - Interview with Roger Espasa
- Fractile Licenses Andes Technology's RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference
Latest News
- Quintauris and Andes Technology Partner to Scale RISC-V Ecosystem
- Europe Achieves a Key Milestone with the Europe’s First Out-of-Order RISC-V Processor chip, with the eProcessor Project
- Intel Unveils Panther Lake Architecture: First AI PC Platform Built on 18A
- TSMC September 2025 Revenue Report
- Andes Technology Hosts First-Ever RISC-V CON in Munich, Powering Next-Gen AI and Automotive Solutions