INICORE annouces availability of optimized IP cores for Actel FPGAs
INICORE annouces availability of optimized IP cores for Actel FPGAs
Santa Clara, March 20, 2001. Inicore today announced that a selection of its easyCORE&tm intellectual property (IP) cores are now available as netlist for the use in the high-performance field programmable gate array (FPGA) devices from Actel Corporation (Nasdaq: ACTL).
The pre-verified easyCORE&tm IP cores are provided as optimized netlists for Actel's FPGAs enabling easy integration into system designs in applications that include telecommunications infrastructure, networking, automotive, military, aerospace and industrial appliances.
While FPGAs continue to offer significant benefits, like time-to-market and flexibility, today's FPGAs are now moving into the traditional ASIC space of high density and high performance - without the ASIC drawbacks of large non-recurring engineering (NRE) costs and up-front volume commitments.
Actel's fine-grained, ASIC-like architectures are ideal for a quick and easy porting of Inicore's IP cores. The easy-to-use cores are well structured, synchronous designed and are tailored to system embedding.
"As SoC designs are becoming more complex and requiring even more verification time, the usage of IP helps to shorten time-to-production," said Hans J. Kuffer, Vice President Business Development from Inicore. "Intellectual Property cores are the foundation for almost any new product development."
"Our long-standing relationship with Inicore has produced the IP cores that enabled customer successes in applications within the aerospace, communications, industrial and consumer markets," said Sunil Baliga, Vice President, Product Marketing at Actel. "Actel is committed to continuing to work with Inicore to offer designers the easy-to-use IP solutions they require."
Inicore's intellectual property (IP) cores are based on a structured design methodology and written in technology-neutral, synchronous VHDL. Each core comes with a testbench, synthesis script and user guide and is verified in a hardware test bed. Designed for ease-of-use and targeted for system-level integration, easyCOREs' are your vehicle to achieve the time-to-market goals.
Licensing and Availability
The following easyCOREs' are currently available as an EDIF Verilog/VHDL netlist: I2C Master, I2C Slave, UART, FastUART, VME and SPI. As VHDL source code: all above plus CAN, CPU (6809 software compatible), HDLC and DSP. All cores can be licensed directly through Inicore. Datasheets can be downloaded from their website at www.inicore.com.
About Inicore:
System-on-Chip from Spec to Silicon
Inicore is a full-service system design house providing FPGA and ASIC solutions, from specification to fully tested silicon. The company's expertise in architectures, intellectual property, methodology and tool handling provides a complete design environment that helps customers shorten their design cycle and speed time to market. Founded in 1986, Inicore has developed more then 200 ASIC and numerous FPGA solutions in the areas of medical instrumentation, data acquisition, industrial and building control, automotive, communications and consumer goods using microcontrollers and DSPs. For more information on Inicore, visit their website at www.inicore.com.
Related Semiconductor IP
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
- Ultra Ethernet Verification IP
Related News
- MoSys Announces Optimized P4 Pipeline Support for Stellar Packet Classification Platform IP for FPGAs
- Lattice Certus-NX FPGAs Optimized for Automotive Applications
- Nextera-Adeas ST 2110 IP cores are now available on Intel FPGAs
- Enhancements to Creonic's DVB-S2X IP Cores for Greater Flexibility and Performance
Latest News
- SiPearl Tapes Out Rhea1 Processor, Closes Series A, Preps Series B
- Thalia Design Automation launches AMALIA Platform 25.2
- Siemens’ Veloce CS selected by Arm for Neoverse Compute Subsystems verification and validation
- InPsytech Tapes Out F2F SoIC Design Compliant with UCIE 2.0 Standard Enabling High-Speed Interconnects for 3D Heterogeneous Integration
- ESD Alliance Reports Electronic System Design Industry Posts $5.1 Billion in Revenue in Q1 2025