InCore Unveils Six-Core RISC-V Test Chip To Accelerate Design Adoption
October 22, 2024 -- InCore Semiconductors is manufacturing a six-core test chip using its proprietary generator technology and provides options for application-specific customizable cores for BLDC motors and smart-card systems, among others. The chip was built using the two core generators that InCore has, said CTO Neel Gala: Azurite and Calcite. He showed how variants of these cores could be generated automatically in order to demonstrate the stability of their technology, which is their key differentiator because it speeds up time-to-market for customers.
The test chip integrates various security IPs and peripherals, which have been demonstrated at SEMICON India with InCore running the Zephyr OS on it-a first for the RISC-V ecosystem. It provides flexibility akin to ARM M0, M1, and M2 cores, wherein users can achieve function toggling without issues.
Larger objectives of InCore involve working with startups on innovative projects and emerging technologies, in accordance with the design-linked incentive or DLI programme. It worked with one DLI-supported startup for coming up with energy meter products. It is working on another one, which deals with AI Chips for telecommunications and 5G/6G applications.
The DLI program has been instrumental in affording startups access to EDA tools, as this saves costs and enables focus on the development of products. Similarly, InCore is participating actively in the policy discussions not only on improving the conditions for better accessibility by startups but also on driving RISC-V adoption in such applications as home automation or next-generation computing.
Related Semiconductor IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
Related News
- Alchip Announces Successful 2nm Test Chip Tapeout
- Jmem Tek and Andes Technology Partner on the World’ s First Quantum-Secure RISC-V Chip
- RISC-V Breakthrough: SpacemiT Develops Server CPU Chip V100 for Next-Generation AI Applications
- Chip Interfaces Successfully Completes Interlaken IP Interoperability Test with Cadence 112G Long-Reach PHY
Latest News
- SEALSQ and IC’Alps Unify Expertise to Deliver Integrated Post-Quantum Cybersecurity and Functional Safety for Autonomous Vehicles
- PUFsecurity’s PUFrt Anchors the Security of Silicon Labs’ SoC to Achieve the Industry’s First PSA Certified Level 4
- The next RISC-V processor frontier: AI
- PQShield joins EU-funded FORTRESS Project: Pioneering Quantum-Safe Secure Boot for Europe’s Digital Future
- PQSecure Achieves NIST CAVP Validation