IBM mulls memory changes to PowerPC

IBM mulls memory changes to PowerPC
By Chris Edwards, EE Times
June 5, 2001 (5:58 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010601S0031

IBM Microelectronics is considering changing the memory architecture in future high-end PowerPC processors to make them more compatible with the embedded processors.

IBM is looking at using the Book E specification in the new processors, although the move would demand changes to operating systems, such as MacOS.

Devised by IBM and Motorola, Book E defines architectural attributes such as the way that the processors handle memory.

Kalpesh Gala, strategic marketing manager for IBM Microelectronics, said: "The 440 is the first Book E processor core. The system-on-chip families are where Book E has begun.

"It is to be decided if Book E is pushed into the high end or if we maintain PowerPC Classic.

"One of the fundamental difficulties is the memory management scheme. Lots of customers use the existing model. They will increase their memory addressability [using the new scheme] but it is a question of whether they will do that."

Sebastien Marineau, netcomm architect for OS supplier QNX, said: "The Book E MMU is quite a bit different from the traditional model but is very close to the 405 and we have ported QNX to that. We anticipate that moving over to Book E would be straightforward. The MMU portion of the OS is a relatively small amount of code."

For its next-generation architecture, IBM is working on a single-chip multiprocessor PowerPC which the company describes as a multicore superscalar design and which will work in symmetric multiprocessor systems.

The multicore processor could run "a single instruction stream or separate instruction schemes", said Gala.

The 1GHz-plus multicore superscalar processor will incorporate a single-instruction, multiple-data engine along the same lines as Motorola's Altivec and support for RapidIO.

"We are talking to customers about what they would like on top of Altivec," said Gala.