Huawei, Altera mix FPGA, memory in 2.5-D device
Rick Merritt, EETimes
11/14/2012 6:59 PM EST
SANTA CLARA, Calif. – Huawei and Altera will package an FPGA and a Wide I/O memory on a 2.5-D silicon interposer to bust through memory bandwidth limits in communications systems. The technology presents thorny challenges but could become critical in networking, said a senior scientist for Huawei.
The new device, in the works only about three months, will significantly reduce board space while increasing performance. “2.5D silicon interposers seem to be the best fit for networking companies—in fact, they are mission critical,” said Anwar A. Mohammed, a senior staff scientist for packaging working in Huawei’s U.S. R&D center here.
To read the full article, click here
Related Semiconductor IP
- Video Tracking FPGA IP core for Xilinx and Altera
- Video Tracking FPGA IP core for Xilinx and Altera
- Video Tracking FPGA IP core for Xilinx and Altera
- SATA Host on Altera Arria II GX
- SATA Device Controller on Altera Arria II GX
Related News
- Altera Starts Production Shipments of Industry’s Highest Memory Bandwidth FPGA
- GOWIN Releases USB 2.0 PHY and Device Controller IP for Their FPGA Products
- System Level Solutions's USB 2.0 Device Controller IP core is now available for Lattice Semiconductor FPGA platform
- Intel Launches Altera, Its New Standalone FPGA Company
Latest News
- Jim Keller: ‘Whatever Nvidia Does, We’ll Do The Opposite’
- FlexGen Streamlines NoC Design as AI Demands Grow
- IntoPIX Presents Its New Titanium Software Suite: Empowering AV-Over-IP Workflows With Speed, Quality & Interoperability
- Global Semiconductor Sales Increase 2.5% Month-to-Month in April
- Speedata Raises $44M to Launch First-Ever Chip Designed Specifically for Accelerating Big Data Analytics - Compute's Second Largest Workload